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參數資料
型號: ADSP-21266
廠商: Analog Devices, Inc.
英文描述: SHARC Embedded Processor
中文描述: SHARC處理器嵌入式處理器
文件頁數: 23/44頁
文件大小: 426K
代理商: ADSP-21266
ADSP-21266
Rev. B
|
Page 23 of 44
|
May 2005
Precision Clock Generator (Direct Pin Routing)
The timing in
Table 18
and
Figure 15
is valid only when the
SRU is configured such that the precision clock generator
(PCG) takes its inputs directly from the DAI pins (via pin buff-
ers) and sends its outputs directly to the DAI pins. For the other
cases where the PCG’s inputs and outputs are not directly
routed to/from DAI pins (via pin buffers) there is no timing
data available. All timing parameters and switching characteris-
tics apply to external DAI pins (DAI_P07 – DAI_P20).
Table 18. Precision Clock Generator (Direct Pin Routing)
Parameter
Timing Requirement
s
t
PCGIW
t
STRIG
t
HTRIG
Min
Max
Unit
Input Clock Pulse Width
PCG Trigger Setup Before Falling Edge of PCG Input Clock
PCG Trigger Hold After Falling Edge of PCG Input Clock
20
2
2
ns
ns
ns
Switching Characteristics
t
DPCGIO
PCG Output Clock and Frame Sync Active Edge Delay After PCG Input
Clock Falling Edge
PCG Output Clock and Frame Sync Delay After PCG Trigger
Output Clock Pulse Width
2.5
2.5 + 2.5 × t
PCGOW
40
10
10 + 2.5 × t
PCGOW
ns
ns
t
DTRIG
t
PCGOW
ns
Figure 15. Precision Clock Generator (Direct Pin Routing)
DAI_Pn
PCG_TRIGx_I
t
STRIG
DAI_Pm
PCG_EXTx_I
(CLKIN)
DAI_Py
PCG_CLKx_O
DAI_Pz
PCG_FSx_O
t
HTRIG
t
DPCGIO
t
DTRIG
t
PCGOW
t
PCGIW
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