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參數資料
型號: ADSP-21266SKSTZ-2B
廠商: ANALOG DEVICES INC
元件分類: 數字信號處理
英文描述: SHARC Embedded Processor
中文描述: 16-BIT, 66.67 MHz, OTHER DSP, PQFP144
封裝: ROHS COMPLIANT, MS-026BFB, LQFP-144
文件頁數: 20/44頁
文件大小: 426K
代理商: ADSP-21266SKSTZ-2B
Rev. B
|
Page 20 of 44
|
May 2005
ADSP-21266
Reset
See
Table 12
and
Figure 9
.
Interrupts
The timing specification in
Table 13
and
Figure 10
applies to the
FLAG0, FLAG1, and FLAG2 pins when they are configured as
IRQ0, IRQ1, and IRQ2 interrupts. Also applies to DAI_P20
1
pins when configured as interrupts.
Core Timer
The timing specification in
Table 14
and
Figure 11
applies to
FLAG3 when it is configured as the core timer (CTIMER).
Table 12. Reset
Parameter
Timing Requirements
t
WRST
t
SRST
Min
4t
CK
8
Max
Unit
ns
ns
RESET Pulse Width Low
1
RESET Setup Before CLKIN Low
1
Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100
μ
s while RESET is low, assuming
stable VDD and CLKIN (not including start-up time of external clock oscillator).
Figure 9. Reset
CLKIN
RESET
t
WRST
t
SRST
Table 13. Interrupts
Parameter
Timing Requirement
t
IPW
Min
2 × t
CCLK
+2
Max
Unit
ns
IRQx Pulse Width
Figure 10. Interrupts
DAI_P20–1
(FLG2–0)
(IRQ2–0)
t
IPW
Table 14. Core Timer
Parameter
Switching Characteristic
t
WCTIM
Min
4 × t
CCLK
– 1
Max
Unit
ns
CTIMER Pulse Width
Figure 11. Core Timer
FLG3
(CTIMER)
t
WCTIM
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