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參數資料
| 型號： | ADSP-21363SBBC-ENG |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數字信號處理 |
| 英文描述： | SHARC Processor |
| 中文描述： | 16-BIT, 55.55 MHz, OTHER DSP, PBGA136 |
| 封裝： | MO-205AE, MBGA-136 |
| 文件頁數： | 1/44頁 |
| 文件大小： | 396K |
| 代理商： | ADSP-21363SBBC-ENG |
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a
Preliminary Technical Data
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
SHARC
Processor
ADSP-21363
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel:781.329.4700
Fax:781.326.8703
2004 Analog Devices, Inc. All rights reserved.
www.analog.com
SUMMARY
High performance 32-bit/40-bit floating point processor
optimized for professional audio processing
At 333 MHz/2 GFLOPs, with unique audio centric peripherals
such as the Digital Audio Interface the ADSP-21363 SHARC
processor is ideal for applications that require industry
leading equalization, reverberation and other effects
processing
Single-Instruction Multiple-Data (SIMD) computational
architecture
Two 32-bit IEEE floating-point/32-bit fixed-point/40-bit
extended precision floating-point computational units,
each with a multiplier, ALU, shifter, and register file
On-chip memory—3M bit of on-chip SRAM and a dedicated
4M bit of on-chip mask-programmable ROM
Code compatible with all other members of the SHARC family
The ADSP-21363 is available with a 333 MHz core instruction
rate. For complete ordering information, see
Ordering
Guide on Page 44
Figure 1. Functional Block Diagram – Processor Core
ADDR
DATA
IOD
ADDR
DATA
IOA
ADDR
DATA
IOA
SRAM
1M BIT
ROM
2M BIT
SRAM
0.5M BIT
BLOCK 0
BLOCK 1
BLOCK 2
BLOCK 3
ADDR
DATA
IOA
IOP REGISTERS
(MEMORY MAPPED)
SEE “ADSP-21363 MEMORY
AND I/O INTERFACE FEATURES”
SECTION FOR DETAILS
I/O PROCESSOR
AND PERIPHERALS
6
JTAG TEST & EMULATION
32
PM ADDRESS BUS
DM ADDRESS BUS
32
PM DATA BUS
DM DATA BUS
64
64
PX REGISTER
PROCESSING
ELEMENT
(PEY)
PROCESSING
ELEMENT
(PEX)
TIMER
INSTRUCTION
CACHE
32 X 48-BIT
DAG1
8X4X32
DAG2
8X4X32
CORE PROCESSOR
PROGRAM
SEQUENCER
SRAM
1M BIT
ROM
2M BIT
SIGNAL
ROUTING
UNIT
SRAM
0.5M BIT
4 BLOCKS OF ON-CHIP MEMORY
IOD
IOA
IOD
IOD
SPI
SPORTS
IDP
PCG
TIMERS
S
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相關代理商/技術參數 |
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| ADSP-21363SBBCZENG | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
| ADSP-21363SBSQ-ENG | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
| ADSP-21363SBSQZENG | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
| ADSP-21363SCSQ-ENG | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
| ADSP-21363SCSQZENG | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
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