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參數資料
| 型號： | ADSP-21363SBBC-ENG |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數字信號處理 |
| 英文描述： | SHARC Processor |
| 中文描述： | 16-BIT, 55.55 MHz, OTHER DSP, PBGA136 |
| 封裝： | MO-205AE, MBGA-136 |
| 文件頁數： | 2/44頁 |
| 文件大小： | 396K |
| 代理商： | ADSP-21363SBBC-ENG |
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Rev. PrA
|
Page 2 of 44
|
September 2004
ADSP-21363
Preliminary Technical Data
KEY FEATURES – PROCESSOR CORE
At 333 MHz (3.0 ns) core instruction rate, the ADSP-21363
performs 2 GFLOPS/666 MMACS
3M bit on-chip single-ported SRAM (1M Bit in blocks 0 and 1,
and 0.50M Bit in blocks 2 and 3) for simultaneous access by
the core processor and DMA
4M bit on-chip mask-programmable ROM (2M bit in block 0
and 2M bit in block 1)
Dual Data Address Generators (DAGs) with modulo and bit-
reverse addressing
Zero-overhead looping with single-cycle loop setup, provid-
ing efficient program sequencing
Single Instruction Multiple Data (SIMD) architecture
provides:
Two computational processing elements
Concurrent execution
Code compatibility with other SHARC family members at
the assembly level
Parallelism in busses and computational units allows sin-
gle cycle executions (with or without SIMD) of a multiply
operation, an ALU operation, a dual memory read or
write, and an instruction fetch
Transfers between memory and core at a sustained 5.4G
bytes/s bandwidth at 333 MHz core instruction rate
INPUT/OUTPUT FEATURES
DMA Controller supports:
25 DMA channels for transfers between ADSP-21363 internal
memory and a variety of peripherals
32-bit DMA transfers at core clock speed, in parallel with full-
speed processor execution
Asynchronous parallel port provides access to asynchronous
external memory
16 multiplexed address/data lines support 24-bit address
external address range with 8-bit data or 16-bit address
external address range with 16-bit data
55M byte per sec transfer rate
External memory access in a dedicated DMA channel
8- to 32- bit and 16- to 32-bit packing options
Programmable data cycle duration options: 2 to 31 CCLK
Digital audio interface (DAI) includes six serial ports, two Pre-
cision Clock Generators, an Input Data Port, three timers,
and a Signal routing unit
Six dual data line serial ports that operate at up to 50M bit/s
on each data line—each has a clock, frame sync and two
data lines that can be configured as either a receiver or
transmitter pair
Left-justified Sample Pair and I
2
S Support, programmable
direction for up to 24 simultaneous receive or transmit
channels using two I
2
S compatible stereo devices per serial
port
TDM support for telecommunications interfaces including
128 TDM channel support for newer telephony interfaces
such as H.100/H.110
Up to 12 TDM stream support, each with 128 channels per
frame
Companding selection on a per channel basis in TDM mode
Input data port provides an additional input path to the
SHARC core, configurable as eight channels of serial data
or seven channels of serial data and a single channel of up
to 20-bit wide parallel data
Signal routing unit provides configurable and flexible con-
nections between all DAI components–six serial ports, two
precision clock generators, an input data port with a data
acquisition port, one SPI port, three timers, 10 interrupts,
six flag inputs, six flag outputs, and 20 SRU I/O pins
(DAI_P20-1)
Two Serial Peripheral Interfaces (SPI): primary on dedicated
pins, secondary on DAI pins provide:
Master or slave serial boot through primary SPI
Full-duplex operation
Master-Slave mode multi-master support
Open drain outputs
Programmable baud rates, clock polarities and phases
3 Muxed Flag/IRQ lines
1 Muxed Flag/Timer expired line
Pulse Width Modulation provides:
16 PWM outputs configured as four groups of four outputs
Supports center-aligned or edge-aligned PWM waveforms
Can generate complementary signals on two outputs in
paired mode or independent signals in non paired mode
PLL has a wide variety of software and hardware multi-
plier/divider ratios
Dual voltage: 3.3 V I/O, 1.2 V core
Available in 136-ball Mini-BGA and 144-lead INT–HS LQFP
Packages (see
Ordering Guide on Page 44
)
相關PDF資料 |
PDF描述 |
|---|---|
| ADSP-21363SBBCZENG | SHARC Processor |
| ADSP-21364 | SHARC Processor |
| ADSP-21364SBBC-ENG | SHARC Processor |
| ADSP-21364SBBCZENG | SHARC Processor |
| ADSP-21364SBSQ-ENG | SHARC Processor |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ADSP-21363SBBCZENG | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
| ADSP-21363SBSQ-ENG | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
| ADSP-21363SBSQZENG | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
| ADSP-21363SCSQ-ENG | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
| ADSP-21363SCSQZENG | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
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