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參數資料
| 型號： | ADSP-21363SBBC-ENG |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數字信號處理 |
| 英文描述： | SHARC Processor |
| 中文描述： | 16-BIT, 55.55 MHz, OTHER DSP, PBGA136 |
| 封裝： | MO-205AE, MBGA-136 |
| 文件頁數： | 3/44頁 |
| 文件大小： | 396K |
| 代理商： | ADSP-21363SBBC-ENG |
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ADSP-21363
Preliminary Technical Data
Rev. PrA
|
Page 3 of 44
|
September 2004
GENERAL DESCRIPTION
The ADSP-21363 SHARC processor is a member of the SIMD
SHARC family of DSPs that feature Analog Devices' Super Har-
vard Architecture. The ADSP-21363 is source code compatible
with the ADSP-2126x, and ADSP-2116x DSPs as well as with
first generation ADSP-2106x SHARC processors in SISD (Sin-
gle-Instruction, Single-Data) mode. The ADSP-21363 is a 32-
bit/40-bit floating point processor optimized for professional
audio applications with a large on-chip SRAM, multiple internal
buses to eliminate I/O bottlenecks, and an innovative Digital
Audio Interface (DAI).
As shown in the functional block diagram
on Page 1
, the
ADSP-21363 uses two computational units to deliver a signifi-
cant performance increase over previous SHARC processors on
a range of signal processing algorithms. Fabricated in a state-of-
the-art, high speed, CMOS process, the ADSP-21363 processor
achieves an instruction cycle time of 3.0 ns at 333 MHz. With its
SIMD computational hardware, the ADSP-21363 can perform 2
GFLOPS running at 333 MHz.
Table 1
shows performance benchmarks for the ADSP-21363.
The ADSP-21363 continues SHARC’s industry leading stan-
dards of integration for DSPs, combining a high performance
32-bit DSP core with integrated, on-chip system features.
The block diagram of the ADSP-21363
on Page 1
, illustrates the
following architectural features:
Two processing elements, each of which comprises an
ALU, Multiplier, Shifter and Data Register File
Data Address Generators (DAG1, DAG2)
Program sequencer with instruction cache
PM and DM buses capable of supporting four 32-bit data
transfers between memory and the core at every core pro-
cessor cycle
Three Programmable Interval Timers with PWM Genera-
tion, PWM Capture/Pulse width Measurement, and
External Event Counter Capabilities
On-Chip SRAM (3M bit)
On-Chip mask-programmable ROM (4M bit)
8- or 16-bit Parallel port that supports interfaces to off-chip
memory peripherals
JTAG test access port
The block diagram of the ADSP-21363
on Page 6
, illustrates the
following architectural features:
DMA controller
Six full duplex serial ports
Two SPI-compatible interface ports—primary on dedi-
cated pins, secondary on DAI pins
Digital Audio Interface that includes two precision clock
generators (PCG), an input data port (IDP), six serial ports,
eight serial interfaces, a 20-bit parallel input port, 10 inter-
rupts, six flag outputs, six flag inputs, three timers, and a
flexible signal routing unit (SRU) and an SPI port
Figure 2 on Page 4
shows one sample configuration of a SPORT
using the precision clock generators to interface with an I
2
S
ADC and an I
2
S DAC with a much lower jitter clock than the
serial port would generate itself. Many other SRU configura-
tions are possible.
ADSP-21363 FAMILY CORE ARCHITECTURE
The ADSP-21363 is code compatible at the assembly level with
the ADSP-2126x, ADSP-21160 and ADSP-21161, and with the
first generation ADSP-2106x SHARC processors. The ADSP-
21363 shares architectural features with the ADSP-2126x and
ADSP-2116x SIMD SHARC processors, as detailed in the fol-
lowing sections.
SIMD Computational Engine
The ADSP-21363 contains two computational processing ele-
ments that operate as a Single-Instruction Multiple-Data
(SIMD) engine. The processing elements are referred to as PEX
and PEY and each contains an ALU, multiplier, shifter and reg-
ister file. PEX is always active, and PEY may be enabled by
setting the PEYEN mode bit in the MODE1 register. When this
mode is enabled, the same instruction is executed in both pro-
cessing elements, but each processing element operates on
different data. This architecture is efficient at executing math
intensive signal processing algorithms.
Entering SIMD mode also has an effect on the way data is trans-
ferred between memory and the processing elements. When in
SIMD mode, twice the data bandwidth is required to sustain
computational operation in the processing elements. Because of
this requirement, entering SIMD mode also doubles the band-
width between memory and the processing elements. When
using the DAGs to transfer data in SIMD mode, two data values
are transferred with each access of memory or the register file.
Independent, Parallel Computation Units
Within each processing element is a set of computational units.
The computational units consist of an arithmetic/logic unit
(ALU), multiplier, and shifter. These units perform all opera-
tions in a single cycle. The three units within each processing
Table 1. ADSP-21363 Benchmarks (at 333 MHz)
Benchmark Algorithm
Speed
(at 333 MHz)
1024 Point Complex FFT (Radix 4, with reversal) 27.9
μ
s
FIR Filter (per tap)
1
IIR Filter (per biquad)
1
Matrix Multiply (pipelined)
[3x3] × [3x1]
[4x4] × [4x1]
Divide (y/×)
Inverse Square Root
1
Assumes two files in multichannel SIMD mode
1.5 ns
6.0 ns
13.5 ns
23.9 ns
10.5 ns
16.3 ns
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相關代理商/技術參數 |
參數描述 |
|---|---|
| ADSP-21363SBBCZENG | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
| ADSP-21363SBSQ-ENG | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
| ADSP-21363SBSQZENG | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
| ADSP-21363SCSQ-ENG | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
| ADSP-21363SCSQZENG | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
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