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參數(shù)資料
| 型號(hào)： | ADSP-21363SBBCZENG |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | SHARC Processor |
| 中文描述： | 16-BIT, 55.55 MHz, OTHER DSP, PBGA136 |
| 封裝： | LEAD FREE, MO-205AE, MBGA-136 |
| 文件頁數(shù)： | 17/44頁 |
| 文件大小： | 396K |
| 代理商： | ADSP-21363SBBCZENG |
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ADSP-21363
Preliminary Technical Data
Rev. PrA
|
Page 17 of 44
|
September 2004
Power-Up Sequencing
The timing requirements for processor startup are given in
Table 10
.
Table 10. Power-Up Sequencing Timing Requirements (Processor Startup)
Parameter
Timing Requirements
t
RSTVDD
t
IVDDEVDD
t
CLKVDD
1
t
CLKRST
t
PLLRST
Min
Max
Unit
RESET Low Before V
DDINT
/V
DDEXT
on
V
DDINT
on Before V
DDEXT
CLKIN Valid After V
DDINT
/V
DDEXT
Valid
CLKIN Valid Before RESET Deasserted
PLL Control Setup Before RESET Deasserted
0
–50
0
10
2
20
3
ns
ms
ms
μs
μs
200
200
Switching Characteristic
t
CORERST
1
Valid V
DDINT
/V
DDEXT
assumes that the supplies are fully ramped to their 1.2 and 3.3 volt rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds
depending on the design of the power supply subsystem.
2
Assumes a stable CLKIN signal, after meeting worst-case startup timing of crystal oscillators. Refer to your crystal oscillator manufacturer's datasheet for startup time.
Assume a 25 ms maximum oscillator startup time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.
3
Based on CLKIN cycles
4
Applies after the power-up sequence is complete. Subsequent resets require a minimum of 4 CLKIN cycles for RESET to be held low in order to properly initialize and
propagate default states at all I/O pins.
5
The 4096 cycle count depends on t
SRST
specification in
Table 12
. If setup time is not met, 1 additional CLKIN cycle may be added to the core reset time, resulting in 4097
cycles maximum.
Core Reset Deasserted After RESET Deasserted
4096t
CK
+ 2 t
CCLK
4, 5
Figure 6. Power Up Sequencing
CLKIN
RESET
t
RSTVDD
RSTOUT
VDDEXT
VDDINT
t
PLLRST
t
CLKRST
t
CLKVDD
t
IVDDEVDD
CLK_CFG1-0
t
CORERST
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| ADSP-21364 | SHARC Processor |
| ADSP-21364SBBC-ENG | SHARC Processor |
| ADSP-21364SBBCZENG | SHARC Processor |
| ADSP-21364SBSQ-ENG | SHARC Processor |
| ADSP-21364SBSQZENG | SHARC Processor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADSP-21363SBSQ-ENG | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
| ADSP-21363SBSQZENG | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
| ADSP-21363SCSQ-ENG | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
| ADSP-21363SCSQZENG | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
| ADSP-21363SKBC-ENG | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
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