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參數資料
型號: ADSP-21363SBBCZENG
廠商: ANALOG DEVICES INC
元件分類: 數字信號處理
英文描述: SHARC Processor
中文描述: 16-BIT, 55.55 MHz, OTHER DSP, PBGA136
封裝: LEAD FREE, MO-205AE, MBGA-136
文件頁數: 8/44頁
文件大小: 396K
代理商: ADSP-21363SBBCZENG
Rev. PrA
|
Page 8 of 44
|
September 2004
ADSP-21363
Preliminary Technical Data
a wide trace for the analog ground (A
VSS
) signal and install a
decoupling capacitor as close as possible to the pin. Note that
the A
VSS
and A
VDD
pins specified in
Figure 4
are inputs to the
processor and not the analog ground plane on the board.
Target Board JTAG Emulator Connector
Analog Devices DSP Tools product line of JTAG emulators uses
the IEEE 1149.1 JTAG test access port of the ADSP-21363 pro-
cessor to monitor and control the target board processor during
emulation. Analog Devices DSP Tools product line of JTAG
emulators provides emulation at full processor speed, allowing
inspection and modification of memory, registers, and proces-
sor stacks. The processor's JTAG interface ensures that the
emulator will not affect target system loading or timing.
For complete information on Analog Devices’ SHARC DSP
Tools product line of JTAG emulator operation, see the appro-
priate “Emulator Hardware User's Guide”.
DEVELOPMENT TOOLS
The ADSP-21363 is supported with a complete set of
CROSSCORE
software and hardware development tools,
including Analog Devices emulators and VisualDSP++
devel-
opment environment. The same emulator hardware that
supports other SHARC processors also fully emulates the
ADSP-21363.
The VisualDSP++ project management environment lets pro-
grammers develop and debug an application. This environment
includes an easy to use assembler (which is based on an alge-
braic syntax), an archiver (librarian/library builder), a linker, a
loader, a cycle-accurate instruction-level simulator, a C/C++
compiler, and a C/C++ runtime library that includes DSP and
mathematical functions. A key point for these tools is C/C++
code efficiency. The compiler has been developed for efficient
translation of C/C++ code to DSP assembly. The SHARC has
architectural features that improve the efficiency of compiled
C/C++ code.
The VisualDSP++ debugger has a number of important fea-
tures. Data visualization is enhanced by a plotting package that
offers a significant level of flexibility. This graphical representa-
tion of user data enables the programmer to quickly determine
the performance of an algorithm. As algorithms grow in com-
plexity, this capability can have increasing significance on the
designer’s development schedule, increasing productivity. Sta-
tistical profiling enables the programmer to non intrusively poll
the processor as it is running the program. This feature, unique
to VisualDSP++, enables the software developer to passively
gather important code execution metrics without interrupting
the real-time characteristics of the program. Essentially, the
developer can identify bottlenecks in software quickly and effi-
ciently. By using the profiler, the programmer can focus on
those areas in the program that impact performance and take
corrective action.
Debugging both C/C++ and assembly programs with the
VisualDSP++ debugger, programmers can:
View mixed C/C++ and assembly code (interleaved source
and object information)
Insert breakpoints
Set conditional breakpoints on registers, memory,
and stacks
Trace instruction execution
Perform linear or statistical profiling of program execution
Fill, dump, and graphically plot the contents of memory
Perform source level debugging
Create custom debugger windows
The VisualDSP++ IDDE lets programmers define and manage
DSP software development. Its dialog boxes and property pages
let programmers configure and manage all of the SHARC devel-
opment tools, including the color syntax highlighting in the
VisualDSP++ editor. This capability permits programmers to:
Control how the development tools process inputs and
generate outputs
Maintain a one-to-one correspondence with the tool’s
command line switches
The VisualDSP++ Kernel (VDK) incorporates scheduling and
resource management tailored specifically to address the mem-
ory and timing constraints of DSP programming. These
capabilities enable engineers to develop code more effectively,
eliminating the need to start from the very beginning, when
developing new application code. The VDK features include
Threads, Critical and Unscheduled regions, Semaphores,
Events, and Device flags. The VDK also supports Priority-based,
Preemptive, Cooperative, and Time-Sliced scheduling
approaches. In addition, the VDK was designed to be scalable. If
the application does not use a specific feature, the support code
for that feature is excluded from the target system.
Because the VDK is a library, a developer can decide whether to
use it or not. The VDK is integrated into the VisualDSP++
development environment, but can also be used via standard
command line tools. When the VDK is used, the development
environment assists the developer with many error-prone tasks
and assists in managing system resources, automating the gen-
eration of various VDK based objects, and visualizing the
system state, when debugging an application that uses the VDK.
VisualDSP++ Component Software Engineering (VCSE) is
Analog Devices’ technology for creating, using, and reusing
software components (independent modules of substantial
functionality) to quickly and reliably assemble software applica-
tions. Download components from the Web and drop them into
Figure 4. Analog Power (A
VDD
) Filter Circuit
V
DDINT
A
VDD
A
VSS
0.01 F
0.1 F
10
相關PDF資料
PDF描述
ADSP-21364 SHARC Processor
ADSP-21364SBBC-ENG SHARC Processor
ADSP-21364SBBCZENG SHARC Processor
ADSP-21364SBSQ-ENG SHARC Processor
ADSP-21364SBSQZENG SHARC Processor
相關代理商/技術參數
參數描述
ADSP-21363SBSQ-ENG 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor
ADSP-21363SBSQZENG 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor
ADSP-21363SCSQ-ENG 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor
ADSP-21363SCSQZENG 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor
ADSP-21363SKBC-ENG 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor
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