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參數(shù)資料
型號(hào)： ADSP-21365SBBCZENG
廠商： ANALOG DEVICES INC
元件分類(lèi)： 數(shù)字信號(hào)處理
英文描述： SHARC Processor
中文描述： 16-BIT, 55.55 MHz, OTHER DSP, PBGA136
封裝： LEAD FREE, MO-205AE, MBGA-136
文件頁(yè)數(shù)： 3/54頁(yè)
文件大小： 559K
代理商： ADSP-21365SBBCZENG
ADSP-21365/6
Preliminary Technical Data
Rev. PrA
|
Page 3 of 54
|
September 2004
GENERAL DESCRIPTION
The ADSP-21365/6 SHARC processors are members of the
SIMD SHARC family of DSPs that feature Analog Devices'
Super Harvard Architecture. The ADSP-21365/6 are source
code compatible with the ADSP-2126x, and ADSP-2116x, DSPs
as well as with first generation ADSP-2106x SHARC processors
in SISD (Single-Instruction, Single-Data) mode. The ADSP-
21365/6 are 32-bit/40-bit floating point processors optimized
for high performance automotive audio applications with its
large on-chip SRAM and mask-programmable ROM, multiple
internal buses to eliminate I/O bottlenecks, and an innovative
Digital Audio Interface (DAI).
As shown in the functional block diagram
on page 1
, the
ADSP-21365/6 uses two computational units to deliver a signif-
icant performance increase over the previous SHARC
processors on a range of signal processing algorithms. Fabri-
cated in a state-of-the-art, high speed, CMOS process, the
ADSP-21365/6 processor achieves an instruction cycle time of
3.0 ns at 333 MHz. With its SIMD computational hardware, the
ADSP-21365/6 can perform 2 GFLOPS running at 333 MHz.
Table 1
shows performance benchmarks for the ADSP-21365/6.
The ADSP-21365/6 continues SHARC’s industry leading stan-
dards of integration for DSPs, combining a high performance
32-bit DSP core with integrated, on-chip system features.
The block diagram of the ADSP-21365/6
on page 1
, illustrates
the following architectural features:
Two processing elements, each of which comprises an
ALU, Multiplier, Shifter and Data Register File
Data Address Generators (DAG1, DAG2)
Program sequencer with instruction cache
PM and DM buses capable of supporting four 32-bit data
transfers between memory and the core at every core pro-
cessor cycle
Three Programmable Interval Timers with PWM Genera-
tion, PWM Capture/Pulse width Measurement, and
External Event Counter Capabilities
On-Chip SRAM (3M bit)
On-Chip mask-programmable ROM (4M bit)
8- or 16-bit Parallel port that supports interfaces to off-chip
memory peripherals
JTAG test access port
The block diagram of the ADSP-21365/6
on page 6
, illustrates
the following architectural features:
DMA controller
Six full duplex serial ports
Two SPI-compatible interface ports—primary on dedi-
cated pins, secondary on DAI pins
Digital Audio Interface that includes two precision clock
generators (PCG), an input data port (IDP), an S/PDIF
receiver/transmitter, eight channels asynchronous sample
rate converters, DTCP cipher, six serial ports, eight serial
interfaces, a 20-bit parallel input port, 10 interrupts, six flag
outputs, six flag inputs, three timers, and a flexible signal
routing unit (SRU) buses
Figure 2 on page 4
shows one sample configuration of a SPORT
using the precision clock generators to interface with an I
2
S
ADC and an I
2
S DAC with a much lower jitter clock than the
serial port would generate itself. Many other SRU configura-
tions are possible.
ADSP-21365/6 FAMILY CORE ARCHITECTURE
The ADSP-21365/6 is code compatible at the assembly level
with the ADSP-2126x, ADSP-21160 and ADSP-21161, and with
the first generation ADSP-2106x SHARC processors. The
ADSP-21365/6 shares architectural features with the ADSP-
2126x and ADSP-2116x SIMD SHARC processors, as detailed
in the following sections.
SIMD Computational Engine
The ADSP-21365/6 contains two computational processing ele-
ments that operate as a Single-Instruction Multiple-Data
(SIMD) engine. The processing elements are referred to as PEX
and PEY and each contains an ALU, multiplier, shifter and reg-
ister file. PEX is always active, and PEY may be enabled by
setting the PEYEN mode bit in the MODE1 register. When this
mode is enabled, the same instruction is executed in both pro-
cessing elements, but each processing element operates on
different data. This architecture is efficient at executing math
intensive signal processing algorithms.
Entering SIMD mode also has an effect on the way data is trans-
ferred between memory and the processing elements. When in
SIMD mode, twice the data bandwidth is required to sustain
computational operation in the processing elements. Because of
this requirement, entering SIMD mode also doubles the band-
width between memory and the processing elements. When
using the DAGs to transfer data in SIMD mode, two data values
are transferred with each access of memory or the register file.
Table 1. ADSP-21365/6 Benchmarks (at 333 MHz)
Benchmark Algorithm
Speed
(at 333 MHz)
1024 Point Complex FFT (Radix 4, with reversal) 27.9
μ
s
FIR Filter (per tap)
1
IIR Filter (per biquad)
1
Matrix Multiply (pipelined)
[3x3] × [3x1]
[4x4] × [4x1]
Divide (y/×)
Inverse Square Root
1
Assumes two files in multichannel SIMD mode
1.5 ns
6.0 ns
13.5 ns
23.9 ns
10.5 ns
16.3 ns
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADSP-21365SBSQ-ENG 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:SHARC Processor
ADSP-21365SBSQZENG 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:SHARC Processor
ADSP-21365SCSQ-ENG 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:SHARC Processor
ADSP-21365SCSQZENG 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:SHARC Processor
ADSP-21365SKBC-ENG 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:SHARC Processor
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