- 您現在的位置：買賣IC網 > PDF目錄374037 > ADSP-BF561SKBCZ500 (ANALOG DEVICES INC) Blackfin Embedded Symmetric Multi-Processor PDF資料下載
參數資料
| 型號： | ADSP-BF561SKBCZ500 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數字信號處理 |
| 英文描述： | Blackfin Embedded Symmetric Multi-Processor |
| 中文描述： | 32-BIT, 500 MHz, OTHER DSP, PBGA256 |
| 封裝： | 12 X 12 MM, ROHS COMPLIANT, MO-225, BGA-256 |
| 文件頁數： | 9/52頁 |
| 文件大小： | 508K |
| 代理商： | ADSP-BF561SKBCZ500 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁當前第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁
ADSP-BF561
Preliminary Technical Data
Rev. PrC
|
Page 9 of 52
|
April 2004
SERIAL PORTS (SPORTS)
The ADSP-BF561 incorporates two dual-channel synchronous
serial ports (SPORT0 and SPORT1) for serial and multiproces-
sor communications. The SPORTs support the following
features:
I
2
S capable operation.
Bidirectional operation – Each SPORT has two sets of inde-
pendent transmit and receive pins, enabling eight channels
of I
2
S stereo audio.
Buffered (8-deep) transmit and receive ports – Each port
has a data register for transferring data words to and from
other DSP components and shift registers for shifting data
in and out of the data registers.
Clocking – Each transmit and receive port can either use an
external serial clock or generate its own, in frequencies
ranging from (f
SCLK
/131,070) Hz to (f
SCLK
/2) Hz.
Word length – Each SPORT supports serial data words
from 3 to 32 bits in length, transferred most-significant-bit
first or least-significant-bit first.
Framing – Each transmit and receive port can run with or
without frame sync signals for each data word. Frame sync
signals can be generated internally or externally, active high
or low, and with either of two pulsewidths and early or late
frame sync.
Companding in hardware – Each SPORT can perform
A-law or μ-law companding according to ITU recommen-
dation G.711. Companding can be selected on the transmit
and/or receive channel of the SPORT without additional
latencies.
DMA operations with single-cycle overhead – Each SPORT
can automatically receive and transmit multiple buffers of
memory data. The DSP can link or chain sequences of
DMA transfers between a SPORT and memory.
Interrupts – Each transmit and receive port generates an
interrupt upon completing the transfer of a data word or
after transferring an entire data buffer or buffers through
DMA.
Multichannel capability – Each SPORT supports 128 chan-
nels out of a 1024-channel window and is compatible with
the H.100, H.110, MVIP-90, and HMVIP standards.
SERIAL PERIPHERAL INTERFACE (SPI) PORTS
The ADSP-BF561 has one SPI-compatible ports that enable the
processor to communicate with multiple SPI-compatible
devices.
The SPI interface uses three pins for transferring data: two data
pins (Master Output-Slave Input, MOSIx, and Master Input-
Slave Output, MISO) and a clock pin (Serial Clock, SCK). One
SPI chip select input pin (SPISS) let other SPI devices select the
DSP, and seven SPI chip select output pins (SPISEL7–1) let the
DSP select other SPI devices. The SPI select pins are reconfig-
ured Programmable Flag pins. Using these pins, the SPI ports
provide a full duplex, synchronous serial interface, which sup-
ports both master and slave modes and multimaster
environments.
Each SPI port’s baud rate and clock phase/polarities are pro-
grammable (see SPI Clock Rate equation), and each has an
integrated DMA controller, configurable to support transmit or
receive data streams. The SPI’s DMA controller can only service
unidirectional accesses at any given time.
During transfers, the SPI ports simultaneously transmit and
receive by serially shifting data in and out on their two serial
data lines. The serial clock line synchronizes the shifting and
sampling of data on the two serial data lines.
UART PORT
The ADSP-BF561 provides a full duplex Universal Asynchro-
nous Receiver/Transmitter (UART) ports (UART0 and
UART1) fully compatible with PC-standard UARTs. The UART
ports provide a simplified UART interface to other peripherals
or hosts, supporting full duplex, DMA supported, asynchronous
transfers of serial data. Each UART port includes support for 5
to 8 data bits; 1 or 2 stop bits; and none, even, or odd parity. The
UART ports support two modes of operation, as follows:
PIO (Programmed I/O) – The processor sends or receives
data by writing or reading I/O-mapped UATX or UARX
registers, respectively. The data is double-buffered on both
transmit and receive.
DMA (Direct Memory Access) – The DMA controller
transfers both transmit and receive data. This reduces the
number and frequency of interrupts required to transfer
data to and from memory. Each UART has two dedicated
DMA channels, one for transmit and one for receive. These
DMA channels have lower priority than most DMA chan-
nels because of their relatively low service rates.
Each UART port’s baud rate (see UART Clock Rate equation),
serial data format, error code generation and status, and inter-
rupts are programmable. In the UART Clock Rate equation, the
divisor (D) can be 1 to 65536.
The UART programmable features include:
Supporting bit rates ranging from (f
SCLK
/ 1048576) to
(f
SCLK
/16) bits per second.
Supporting data formats from 7 to12 bits per frame.
Both transmit and receive operations can be configured to
generate maskable interrupts to the processor.
In conjunction with the general-purpose timer functions, auto-
baud detection is supported.
SPI Clock Rate
SPIBAUD
2
×
----------------------------------
=
UART Clock Rate
16
D
×
---------------
=
相關PDF資料 |
PDF描述 |
|---|---|
| ADSP-BF561 | Synchronous 4-Bit Up/Down Binary Counters With Dual Clock and Clear 16-PDIP 0 to 70 |
| ADSP-BF561SBB500 | Blackfin Embedded Symmetric Multi-Processor |
| ADSP21020 | 32/40-Bit IEEE Floating-Point DSP Microprocessor |
| ADSP-21020BG-100 | 32/40-Bit IEEE Floating-Point DSP Microprocessor |
| ADSP2184 | 16 A SPDT MINIATURE POWER RELAY |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ADSP-BF561SKBCZ-5A | 功能描述:IC DSP CTLR 32BIT BKFN 256CSPBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數字式信號處理器） 系列:Blackfin® 標準包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，FCBGA 供應商設備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP-BF561SKBCZ-5V | 功能描述:IC DSP 32BIT 500MHZ 256CSPBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數字式信號處理器） 系列:Blackfin® 標準包裝:2 系列:StarCore 類型:SC140 內核 接口:DSI，以太網，RS-232 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，FCBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-BF561SKBCZ600 | 制造商:Analog Devices 功能描述:DSP FIX PT 16BIT 600MHZ 600MIPS 256CSPBGA - Trays 制造商:Analog Devices 功能描述:IC MULTI-PROCESSOR |
| ADSP-BF561SKBCZ-6A | 功能描述:IC DSP CTRLR 32B 600MHZ 256CPBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數字式信號處理器） 系列:Blackfin® 標準包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，FCBGA 供應商設備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP-BF561SKBCZ-6A | 制造商:Analog Devices 功能描述:Digital Signal Processor IC |
發布緊急采購，3分鐘左右您將得到回復。