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參數(shù)資料
型號(hào)： ADSP-BF561SKBCZ600
廠商： ANALOG DEVICES INC
元件分類(lèi)： 數(shù)字信號(hào)處理
英文描述： Blackfin Embedded Symmetric Multi-Processor
中文描述： 32-BIT, 133 MHz, OTHER DSP, PBGA256
封裝： 12 X 12 MM, LEAD FREE, MO-225, MBGA-256
文件頁(yè)數(shù)： 15/52頁(yè)
文件大小： 508K
代理商： ADSP-BF561SKBCZ600
ADSP-BF561
Preliminary Technical Data
Rev. PrC
|
Page 15 of 52
|
April 2004
Fill, dump, and graphically plot the contents of memory
Perform source level debugging
Create custom debugger windows
The VisualDSP++ IDE lets programmers define and manage
software development. Its dialog boxes and property pages let
programmers configure and manage all development tools,
including Color Syntax Highlighting in the VisualDSP++ edi-
tor. These capabilities permit programmers to:
Control how the development tools process inputs and
generate outputs.
Maintain a one-to-one correspondence with the tool’s
command line switches.
The VisualDSP++ Kernel (VDK) incorporates scheduling and
resource management tailored specifically to address the mem-
ory and timing constraints of embedded, real-time
programming. These capabilities enable engineers to develop
code more effectively, eliminating the need to start from the
very beginning, when Developing new application code. The
VDK features include Threads, Critical and Unscheduled
regions, Semaphores, Events, and Device flags. The VDK also
supports Priority-based, Pre-emptive, Cooperative and Time-
Sliced scheduling approaches. In addition, the VDK was
designed to be scalable. If the application does not use a specific
feature, the support code for that feature is excluded from the
target system.
Because the VDK is a library, a developer can decide whether to
use it or not. The VDK is integrated into the VisualDSP++
development environment, but can also be used with standard
command-line tools. When the VDK is used, the development
environment assists the developer with many error-prone tasks
and assists in managing system resources, automating the gen-
eration of various VDK based objects, and visualizing the
system state, when debugging an application that uses the VDK.
VCSE is Analog Devices technology for creating, using, and
reusing software components (independent modules of sub-
stantial functionality) to quickly and reliably assemble software
applications. Download components from the Web and drop
them into the application. Publish component archives from
within VisualDSP++. VCSE supports component implementa-
tion in C/C++ or assembly language.
Use the Expert Linker to visually manipulate the placement of
code and data on the embedded system. View memory utiliza-
tion in a color-coded graphical form, easily move code and data
to different areas of the processor or external memory with the
drag of the mouse, examine run time stack and heap usage. The
Expert Linker is fully compatible with existing Linker Definition
File (LDF), allowing the developer to move between the graphi-
cal and textual environments.
Analog Devices’ emulators use the IEEE 1149.1 JTAG test access
port of the ADSP-BF561 to monitor and control the target
board processor during emulation. The emulator provides full-
speed emulation, allowing inspection and modification of mem-
ory, registers, and processor stacks. Non intrusive in-circuit
emulation is assured by the use of the processor’s JTAG inter-
face—the emulator does not affect target system loading or
timing.
In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide
range of tools supporting the Blackfin processor family. Third
Party software tools include DSP libraries, real-time operating
systems, and block diagram design tools.
DESIGNING AN EMULATOR-COMPATIBLE
PROCESSOR BOARD (TARGET)
The Analog Devices family of emulators are tools that every sys-
tem developer needs to test and debug hardware and software
systems. Analog Devices has supplied an IEEE 1149.1 JTAG
Test Access Port (TAP) on the ADSP-BF561. The emulator uses
the TAP to access the internal features of the processor, allow-
ing the developer to load code, set breakpoints, observe
variables, observe memory, and examine registers. The proces-
sor must be halted to send data and commands, but once an
operation has been completed by the emulator, the processor is
set running at full speed with no impact on system timing.
To use these emulators, the target board must include a header
that connects the processor’s JTAG port to the emulator.
For details on target board design issues including mechanical
layout, single processor connections, multiprocessor scan
chains, signal buffering, signal termination, and emulator pod
logic, see the
EE-68: Analog Devices JTAG Emulation Technical
Reference
www.analog.com
to keep pace with improvements to emulator support.
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