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參數資料
| 型號： | ADSP-BF561SKBCZ600 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數字信號處理 |
| 英文描述： | Blackfin Embedded Symmetric Multi-Processor |
| 中文描述： | 32-BIT, 133 MHz, OTHER DSP, PBGA256 |
| 封裝： | 12 X 12 MM, LEAD FREE, MO-225, MBGA-256 |
| 文件頁數： | 43/52頁 |
| 文件大小： | 508K |
| 代理商： | ADSP-BF561SKBCZ600 |
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ADSP-BF561
Preliminary Technical Data
Rev. PrC
|
Page 43 of 52
|
April 2004
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high impedance state to the point when they
start driving. The output enable time t
ENA
is the interval from
the point when a reference signal reaches a high or low voltage
level to the point when the output starts driving as shown in the
Output Enable/Disable diagram (
Figure 24
). The time
t
ENA_MEASURED
is the interval from when the reference signal
switches to when the output voltage reaches 2.0V (output high)
or 1.0V (output low). Time t
TRIP
is the interval from when the
output starts driving to when the output reaches the 1.0V or
2.0V trip voltage. Time t
ENA
is calculated as
t
ENA_MEASURED
–t
TRIP
. If multiple pins (such as the data bus) are
enabled, the measurement value is that of the first pin to start
driving.
Output Disable Time
Output pins are considered to be disabled when they stop driv-
ing, go into a high impedance state, and start to decay from their
output high or low voltage. The time for the voltage on the bus
to decay by V is dependent on the capacitive load, C
L
and the
load current, I
L
. This decay time can be approximated by the
following equation:
The output disable time t
DIS
is the difference between
t
DIS_MEASURED
and t
DECAY
as shown in
Figure 24
.The time
t
DIS_MEASURED
is the interval from when the reference signal
switches to when the output voltage decays V from the mea-
sured output high or output low voltage. t
DECAY
is calculated
with test loads C
L
and I
L
, and with V equal to 0.5 V.
EXAMPLE SYSTEM HOLD TIME CALCULATION
To determine the data output hold time in a particular system,
first calculate t
DECAY
using the equation given above. Choose
V to be the difference between the ADSP-BF561's output volt-
age and the input threshold for the device requiring the hold
time. A typical V will be 0.4 V. CL is the total bus capacitance
(per data line), and IL is the total leakage or three-state current
(per data line). The hold time will be t
DECAY
plus the minimum
disable time (i.e., t
DSDAT
for an SDRAM write cycle).
Figure 24. Output Enable/Disable
t
DECAY
C
L
V
(
)
I
L
=
REFERENCE
SIGNAL
t
DIS
OUTPUT STARTS DRIVING
V
OH
(MEASURED) -
V
V
OL
(MEASURED) +
V
t
DIS-MEASURED
V
OH
(MEASURED)
V
OL
(MEASURED)
2.0V
1.0V
V
OH
(MEASURED)
V
OL
(MEASURED)
t
TRIP
HIGH-IMPEDANCE STATE.
TEST CONDITIONS CAUSE THIS
VOLTAGE TO BE APPROXIMATELY 1.5V.
OUTPUT STOPS DRIVING
t
ENA
t
DECAY
t
ENA-MEASURED
Figure 25. Typical Output Delay or Hold vs. Load Capacitance (at Max Case
Temperature)
LOAD CAPACITANCE - pF
5
-5
0
210
30
60
90
120
150
180
4
3
2
1
NOMINAL
O
TBD
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相關代理商/技術參數 |
參數描述 |
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| ADSP-BF561SKBCZC70 | 制造商:Analog Devices 功能描述: |
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