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參數資料
型號: ADT7463ARQZ-REEL
廠商: ON Semiconductor
文件頁數: 14/50頁
文件大小: 726K
描述: IC REMOTE THERMAL CTRLR 24-QSOP
產品變化通告: MFG CHG Notification ADI to ON Semi
QSOP 24ld Pkg (MSL) Change 17/Jun/2010
標準包裝: 2,500
系列: dBCool®
功能: 風扇控制,溫度監控器
傳感器類型: 內部和外部
感應溫度: -40°C ~ 120°C,外部傳感器
精確度: ±1.5°C(最小值)
拓撲: ADC,比較器,風扇速度計數器,多路復用器,寄存器庫
輸出類型: SMBus?
輸出警報:
輸出風扇:
電源電壓: 3 V ~ 5.5 V
工作溫度: -40°C ~ 120°C
安裝類型: 表面貼裝
封裝/外殼: 24-SSOP(0.154",3.90mm 寬)
供應商設備封裝: 24-QSOP
包裝: 帶卷 (TR)
ADT7463
http://onsemi.com
14
ADT7463 Read Operations
The ADT7463 uses the following SMBus read protocols.
Receive Byte
This is useful when repeatedly reading a single register.
The register address needs to have been set up previously. In
this operation, the master device receives a single byte from
a slave device as follows:
1. The master device asserts a start condition on SDA
2. The master sends the 7bit slave address followed
by the read bit (high)
3. The addressed slave device asserts ACK on SDA
4. The master receives a data byte
5. The master asserts NO ACK on SDA
6. The master asserts a stop condition on SDA and
the transaction ends
In the ADT7463, the receive byte protocol is used to read
a single byte of data from a register whose address has
previously been set by a send byte or write byte operation.
Figure 22. Single Byte Read from a Register
SLAVE
ADDRESS
DATA
A
R
S
A  P
2
4
3
1
5   6
Alert Response Address
Alert response address (ARA) is a feature of SMBus
devices that allows an interrupting device to identify itself
to the host when multiple devices exist on the same bus.
The SMBALERT
  output can be used as an interrupt
output or can be used as an SMBALERT
. One or more
outputs can be connected to a common SMBALERT
 line
connected to the master. If a devices SMBALERT
 line goes
low, the following procedure occurs:
1. SMBALERT
 is pulled low
2. Master initiates a read operation and sends the
alert response address (ARA = 0001 100). This is
a general call address that must not be used as a
specific device address
3. The device whose SMBALERT
 output is low
responds to the alert response address, and the
master reads its device address. The address of the
device is now known and it can be interrogated in
the usual way
4. If more than one devices SMBALER
T output is
low, the one with the lowest device address will
have priority in accordance with normal SMBus
arbitration
5. Once the ADT7463 has responded to the alert
response address, the master must read the status
registers and the SMBALERT
 will only be cleared
if the error condition has gone away
SMBus Timeout
The ADT7463 includes an SMBus timeout feature. If
there is no SMBus activity for 35 ms, the ADT7463 assumes
that the bus is locked and releases the bus. This prevents the
device from locking or holding the SMBus expecting data.
Some SMBus controllers cannot handle the SMBus timeout
feature, so it can be disabled.
Table 6. CONFIGURATION REGISTER 1 (REG. 0X40)
Bit
Description
<6> TODIS
0: SMBus Timeout Enabled (Default)
<6> TODIS
1: SMBus Timeout Disabled
Voltage Measurement Inputs
The ADT7463 has four external voltage measurement
channels. It can also measure its own supply voltage, V
CC
.
Pins 20 to 23 are dedicated to measuring 5 V, 12 V, and
2.5 V supplies and the processor core voltage V
CCP
 (0 V to
3 V input). The V
CC
 supply voltage measurement is carried
out through the V
CC
  pin (Pin 4). Setting Bit 7 of
Configuration Register 1 (Reg. 0x40) allows a 5 V supply to
power the ADT7463 and be measured without overranging
the V
CC
 measurement channel. The 2.5 V input can be used
to monitor a chipset supply voltage in computer systems.
AnalogtoDigital Converter (ADC)
All analog inputs are multiplexed into the onchip,
successive approximation, ADC. This has a resolution of
10 bits. The basic input range is 0 V to 2.25 V, but the inputs
have builtin attenuators to allow measurement of 2.5 V,
3.3 V, 5 V, 12 V, and the processor core voltage V
CCP
without any external components. To allow for the tolerance
of these supply voltages, the ADC produces an output of 3/4
full scale (decimal 768 or 300 hex) for the nominal input
voltage and so has adequate headroom to cope with
overvoltages.
Input Circuitry
The internal structure for the analog inputs is shown in
Figure 23. Each input circuit consists of an input protection
diode, an attenuator, plus a capacitor to form a firstorder,
lowpass filter that gives the input immunity to high
frequency noise.
Table 7. VOLTAGE MEASUREMENT REGISTERS
Register
Description
Default
0x20
2.5 V Reading
0x00
0x21
V
CCP
 Reading
0x00
0x22
V
CC
 Reading
0x00
0x23
5 V Reading
0x00
0x24
12 V Reading
0x00
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