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參數資料
型號: ADT7463ARQZ-REEL
廠商: ON Semiconductor
文件頁數: 39/50頁
文件大小: 726K
描述: IC REMOTE THERMAL CTRLR 24-QSOP
產品變化通告: MFG CHG Notification ADI to ON Semi
QSOP 24ld Pkg (MSL) Change 17/Jun/2010
標準包裝: 2,500
系列: dBCool®
功能: 風扇控制,溫度監控器
傳感器類型: 內部和外部
感應溫度: -40°C ~ 120°C,外部傳感器
精確度: ±1.5°C(最小值)
拓撲: ADC,比較器,風扇速度計數器,多路復用器,寄存器庫
輸出類型: SMBus?
輸出警報:
輸出風扇:
電源電壓: 3 V ~ 5.5 V
工作溫度: -40°C ~ 120°C
安裝類型: 表面貼裝
封裝/外殼: 24-SSOP(0.154",3.90mm 寬)
供應商設備封裝: 24-QSOP
包裝: 帶卷 (TR)
ADT7463
http://onsemi.com
39
Table 53. REGISTER 0X40  CONFIGURATION REGISTER 1 (POWERON DEFAULT = 0X00)
Bit
Name
R/W
Description
<0>
STRT
R/W
Logic 1 enables monitoring and PWM control outputs based on the limit settings programmed.
Logic 0 disables monitoring and PWM control based on the default powerup limit settings.
Note that the limit values programmed are preserved even if a Logic 0 is written to this bit and
the default settings are enabled. This bit becomes readonly and cannot be changed once Bit 1
(LOCK bit) has been written. All limit registers should be programmed by BIOS before setting
this bit to 1. (Lockable.)
<1>
LOCK
Write
Once
Logic 1 locks all limit values to their current settings. Once this bit is set, all lockable registers
become readonly and cannot be modified until the ADT7463 is powered down and powered
up again. This prevents rogue programs such as viruses from modifying critical system limit
settings. (Lockable.)
<2>
RDY
Readonly
This bit is set to 1 by the ADT7463 to indicate that the device is fully poweredup and ready to
begin systems monitoring.
<3>
FSPD
R/W
When set to 1, all fans run at full speed. Poweron default = 0. (This bit cannot be locked.)
<4>
V ?I
R/W
BIOS should set this bit to a 1 when the ADT7463 is configured to measure current from an
ADI ADOPTt VRM controller and measure the CPUs core voltage. This allows monitoring
software to display CPU watts usage. (Lockable.)
<5>
FSPDIS
R/W
Logic 1 disables fan spinup for two TACH pulses. Instead, the PWM outputs go high for the
entire fan spinup timeout selected.
<6>
TODIS
R/W
When set to 1, the SMBus timeout feature is disabled. This allows the ADT7463 to be used with
SMBus controllers that cannot handle SMBus timeouts. (Lockable.)
<7>
V
CC
R/W
When set to 1, the ADT7463 rescales its V
CC
 pin to measure a 5.0 V supply.
When set to 0, the ADT7463 measures V
CC
 as a 3.3 V supply. (Lockable.)
Table 54. REGISTER 0X41  INTERRUPT STATUS REGISTER 1 (POWERON DEFAULT = 0X00)
Bit
Name
R/W
Description
<0>
2.5V
Readonly
A 1 indicates that the 2.5 V high or low limit has been exceeded. This bit is cleared on a read of
the status register only if the error condition has subsided.
<1>
V
CCP
Readonly
A 1 indicates the V
CCP
 high or low limit has been exceeded. This bit gets cleared on a read of
the status register only if the error condition has subsided.
<2>
V
CC
Readonly
A 1 indicates that the V
CC
 high or low limit has been exceeded. This bit is cleared on a read of
the status register only if the error condition has subsided.
<3>
5V
Readonly
A 1 indicates the 5 V high or low limit has been exceeded. This bit gets cleared on a read of the
status register only if the error condition has subsided.
<4>
R1T
Readonly
A 1 indicates that the Remote 1 Low or High temperature limit has been exceeded. This bit is
cleared on a read of the status register only if the error condition has subsided.
<5>
LT
Readonly
A 1 indicates the Local Low or High temperature limit has been exceeded. This bit is cleared on
a read of the Status Register only if the error condition has subsided.
<6>
R2T
Readonly
A 1 indicates that the Remote 2 Low or High temperature limit has been exceeded. This bit is
cleared on a read of the status register only if the error condition has subsided.
<7>
OOL
Readonly
A 1 indicates that an outoflimit event has been latched in Status Register 2. This bit is a
logical OR of all status bits in Status Register 2. Software can test this bit in isolation to
determine whether any of the voltage, temperature, or fan speed readings represented by
Status Register 2 are outoflimit. This saves the need to read Status Register 2 every interrupt
or polling cycle.
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