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參數(shù)資料
型號: ADT7463ARQZ-REEL
廠商: ON Semiconductor
文件頁數(shù): 42/50頁
文件大小: 726K
描述: IC REMOTE THERMAL CTRLR 24-QSOP
產(chǎn)品變化通告: MFG CHG Notification ADI to ON Semi
QSOP 24ld Pkg (MSL) Change 17/Jun/2010
標(biāo)準(zhǔn)包裝: 2,500
系列: dBCool®
功能: 風(fēng)扇控制,溫度監(jiān)控器
傳感器類型: 內(nèi)部和外部
感應(yīng)溫度: -40°C ~ 120°C,外部傳感器
精確度: ±1.5°C(最小值)
拓?fù)洌?/td> ADC,比較器,風(fēng)扇速度計(jì)數(shù)器,多路復(fù)用器,寄存器庫
輸出類型: SMBus?
輸出警報:
輸出風(fēng)扇:
電源電壓: 3 V ~ 5.5 V
工作溫度: -40°C ~ 120°C
安裝類型: 表面貼裝
封裝/外殼: 24-SSOP(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 24-QSOP
包裝: 帶卷 (TR)
ADT7463
http://onsemi.com
42
Table 61. PWM CONFIGURATION REGISTER BITS
Bit
Name
R/W
Description
<2:0>
SPIN
R/W
These bits control the startup timeout for PWMx. The PWM output stays high until two valid
TACH rising edges are seen from the fan. If there is not a valid TACH signal during the fan
TACH measurement directly after the fan startup timeout period, the TACH measurement
reads 0xFFFF and Status Register 2 reflects the fan fault. If the TACH Minimum High and Low
Byte contains 0xFFFF or 0x0000, the Status Register 2 Bit is not set, even if the fan has not
started.
000 = No Startup Timeout
001 = 100 ms
010 = 250 ms (Default)
011 = 400 ms
100 = 667 ms
101 = 1 s
110 = 2 s
111 = 4 s
<3>
SLOW
R/W
SLOW = 1 makes the ramp rates for acoustic enhancement four times longer.
<4>
INV
R/W
This bit inverts the PWM output. The default is 0, which corresponds to a logic high output for
100% duty cycle. Setting this bit to 1 inverts the PWM output, so 100% duty cycle corresponds
to a logic low output.
<7:5>
BHVR
R/W
These bits assign each fan to a particular temperature sensor for localized cooling.
000 = Remote 1 Temperature controls PWMx (Automatic Fan Control Mode).
001 = Local Temperature controls PWMx (Automatic Fan Control Mode).
010 = Remote 2 Temperature controls PWMx (Automatic Fan Control Mode).
011 = PWMx runs full speed (Default).
100 = PWMx is disabled.
101 = Fastest speed calculated by Local and Remote 2 Temperature Control PWMx.
110 = Fastest speed calculated by all three Temperature Channels Control PWMx.
111 = Manual Mode. PWM duty cycle registers (Reg. 0x300x32) become writable.
Table 62. TEMP T
RANGE
/PWM FREQUENCY REGISTERS (POWERON DEFAULT = 0XC4) (Note 1)
Register Address
R/W
Description
0x5F
R/W
Remote 1 T
RANGE
/PWM1 Frequency
0x60
R/W
Local Temp T
RANGE
/PWM2 Frequency
0x61
R/W
Remote 2 T
RANGE
/PWM3 Frequency
1.  These registers become readonly when the Configuration Register 1 Lock bit is set to 1. Further attempts to write to the is register have no
effect.
Table 63. TEMP T
RANGE
/PWM FREQUENCY REGISTER BITS
Bit
Name
R/W
Description
<2:0>
FREQ
R/W
These bits control the PWMx frequency.
000 = 11.0 Hz
001 = 14.7 Hz
010 = 22.1 Hz
011 = 29.4 Hz
100 = 35.3 Hz (Default)
101 = 44.1 Hz
110 = 58.8 Hz
111 = 88.2 Hz
<3>
THRM
R/W
THRM = 1 causes the THERM
 pin (Pin 14 or Pin 20) to assert low as an output when this
temperature channels THERM
 limit is exceeded by 0.25癈. The THERM
 pin remains asserted
until the temperature is equal to or below the THERM
 limit. The minimum time that THERM
asserts for is one monitoring cycle. This allows clock modulation of devices that incorporate this
feature.
THRM = 0 makes the THERM
 pin act as an input only, for example, for Pentium
?/DIV>
4 PROCHOT
monitoring, when Pin 14 or Pin 20 is configured as THERM
.
<7:4>
RANGE
R/W
These bits determine the PWM duty cycle vs. temperature slope for automatic fan control.
0000 = 2癈
0001 = 2.5癈
0010 = 3.33癈
0011 = 4癈
0100 = 5癈
0101 = 6.67癈
0110 = 8癈
0111 = 10癈
1000 = 13.33癈
1001 = 16癈
1010 = 20癈
1011 = 26.67癈
1100 = 32癈 (Default)
1101 = 40癈
1110 = 53.33癈
1111 = 80癈
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