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參數(shù)資料
型號(hào): ADT7482ARMZ-REEL
廠商: ON Semiconductor
文件頁(yè)數(shù): 13/20頁(yè)
文件大小: 282K
描述: IC SENSOR TEMP 2CH ALARM 10MSOP
產(chǎn)品變化通告: MFG CHG Notification ADI to ON Semi
標(biāo)準(zhǔn)包裝: 3,000
功能: 溫度監(jiān)控系統(tǒng)(傳感器)
傳感器類(lèi)型: 內(nèi)部和外部
感應(yīng)溫度: -40°C ~ 125°C,外部傳感器
精確度: ±2.5°C(最小值)
拓?fù)洌?/td> ADC,比較器,多路復(fù)用器,寄存器庫(kù)
輸出類(lèi)型: SMBus?
輸出警報(bào):
輸出風(fēng)扇:
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 125°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 10-MSOP
包裝: 帶卷 (TR)
ADT7482
http://onsemi.com
13
Table 16. LIST OF REGISTERS (continued)
Read
Address
(Hex)
Lock
Comment
Power-On Default
Mnemonic
Write
Address
(Hex)
14
14
Remote 2 Temperature Low Limit Low Byte
0000 0000
Bit 3 Conf. Reg. = 1
Yes
19
19
Remote 1 THERM
 Limit
0101 0101 (0x55) (85癈)
Bit 3 Conf. Reg. = 0
Yes
19
19
Remote 2 THERM
 Limit
0101 0101 (0x55) (85癈)
Bit 3 Conf. Reg. = 1
Yes
20
20
Local THERM
 Limit
0101 0101 (0x55) (85癈)
Yes
21
21
THERM
 Hysteresis
0000 1010 (0x0A) (10癈)
Yes
22
22
Consecutive ALERT
0000 0001 (0x01)
Yes
23
N/A
Status Register 2
0000 0000 (0x00)
No
24
24
Configuration 2 Register
0000 0000 (0x00)
Yes
30
N/A
Remote 2 Temperature Value High Byte
0000 0000 (0x00)
No
31
31
Remote 2 Temperature High Limit High Byte
0101 0101 (0x55) (85癈)
Yes
32
32
Remote 2 Temperature Low Limit High Byte
0000 0000 (0x00) (0癈)
Yes
33
N/A
Remote 2 Temperature Value Low Byte
0000 0000 (0x00)
No
34
34
Remote 2 Temperature Offset High Byte
0000 0000 (0x00)
Yes
35
35
Remote 2 Temperature Offset Low Byte
0000 0000 (0x00)
Yes
36
36
Remote 2 Temperature High Limit Low Byte
0000 0000 (0x00) (0癈)
Yes
37
37
Remote 2 Temperature Low Limit Low Byte
0000 0000 (0x00) (0癈)
Yes
39
39
Remote 2 THERM
 Limit
0101 0101 (0x55) (85癈)
Yes
FE
N/A
Manufacturer ID
0100 0001 (0x41)
N/A
FF
N/A
Die Revision Code
0110 0101 (0x65)
N/A
1.  Writing to address 0F causes the ADT7482 to perform a single measurement. It is not a data register as such and it does not matter what
data is written to it.
Serial Bus Interface
Control of the ADT7482 is achieved via the serial bus.
The ADT7482 is connected to this bus as a slave device,
under the control of a master device.
The ADT7482 has an SMBus timeout feature. When this is
enabled, the SMBus times out after typically 25 ms of no
activity. However, this feature is not enabled by default. Set
Bit 7 (SCL Timeout Bit) of the consecutive alert register
(Address = 0x22) to enable the SCL Timeout. Set Bit 6 (SDA
Timeout Bit) of the consecutive alert register (Address = 0x22)
to enable the SDA Timeout.
Consult the SMBus 1.1 Specification for more information
(www.smbus.org
).
Addressing the Device
In general, every SMBus device has a 7-bit device
address, except for some devices that have extended, 10-bit
addresses. When the master device sends a device address
over the bus, the slave device with that address responds.
The ADT7482 is available with one device address, 0x4C
(1001 100b). The address mentioned in this data sheet is a
7-bit address. The R/W
 bit needs to be added to arrive at an
8-bit address.
Serial Bus Protocol Operation
The master initiates data transfer by establishing a start
condition, defined as a high-to-low transition on the serial
data line SDATA while the serial clock line SCLK remains
high. This indicates that an address/data stream follows.
All slave peripherals connected to the serial bus respond
to the start condition and shift in the next eight bits,
consisting of a 7-bit address (MSB first) plus an R/W
 bit,
which determines the direction of the data transfer, that is,
whether data is to be written to or read from the slave device.
The peripheral whose address corresponds to the transmitted
address responds by pulling the data line low during the low
period before the ninth clock pulse, known as the
acknowledge bit. All other devices on the bus now remain
idle while the selected device waits for data to be read from
or written to it. If the R/W
 bit is a 0, the master writes to the
slave device. If the R/W
 bit is a 1, the master reads from the
slave device.
Data is sent over the serial bus in a sequence of nine clock
pulses, eight bits of data followed by an acknowledge bit
from the slave device. Transitions on the data line must
occur during the low period of the clock signal and remain
stable during the high period, since a low-to-high transition
when the clock is high can be interpreted as a stop signal. The
number of data bytes that can be transmitted over the serial
bus in a single read or write operation is limited only by what
the master and slave devices can handle.
When all data bytes have been read or written, stop
conditions are established. In write mode, the master pulls
the data line high during the tenth clock pulse to assert a stop
condition. In read mode, the master device overrides the
acknowledge bit by pulling the data line high during the low
period before the ninth clock pulse. This is known as no
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