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參數資料
| 型號： | ADUC842BCP32-3 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MicroConverter 12-Bit ADCs and DACs with Embedded High Speed 62-kB Flash MCU |
| 中文描述： | 8-BIT, FLASH, 8.38 MHz, MICROCONTROLLER, QCC56 |
| 封裝： | 8 X 8 MM, LEAD FRAME, MO-220VLLD2, CSP-56 |
| 文件頁數： | 61/88頁 |
| 文件大小： | 903K |
| 代理商： | ADUC842BCP32-3 |
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ADuC841/ADuC842/ADuC843
TCON
SFR Address
Power-On Default
Bit Addressable
Rev. 0 | Page 61 of 88
Timer/Counter 0 and 1
Control Register
88H
00H
Yes
Table 29. TCON SFR Bit Designations
Bit No.
Name
7
TF1
Description
Timer 1 Overflow Flag.
Set by hardware on a Timer/Counter 1 overflow.
Cleared by hardware when the program counter (PC) vectors to the interrupt service routine.
Timer 1 Run Control Bit.
Set by the user to turn on Timer/Counter 1.
Cleared by the user to turn off Timer/Counter 1.
Timer 0 Overflow Flag.
Set by hardware on a Timer/Counter 0 overflow.
Cleared by hardware when the PC vectors to the interrupt service routine.
Timer 0 Run Control Bit.
Set by the user to turn on Timer/Counter 0.
Cleared by the user to turn off Timer/Counter 0.
External Interrupt 1 (INT1) Flag.
Set by hardware by a falling edge or by a zero level being applied to the external interrupt pin, INT1, depending on
the state of Bit IT1.
Cleared by hardware when the PC vectors to the interrupt service routine only if the interrupt was transition-
activated. If level-activated, the external requesting source controls the request flag, rather than the on-chip
hardware.
External Interrupt 1 (IE1) Trigger Type.
Set by software to specify edge-sensitive detection, i.e., 1-to-0 transition.
Cleared by software to specify level-sensitive detection, i.e., zero level.
External Interrupt 0 (INT0) Flag.
Set by hardware by a falling edge or by a zero level being applied to external interrupt pin INT0, depending on the
state of Bit IT0.
Cleared by hardware when the PC vectors to the interrupt service routine only if the interrupt was transition-
activated. If level-activated, the external requesting source controls the request flag, rather than the on-chip
hardware.
External Interrupt 0 (IE0) Trigger Type.
Set by software to specify edge-sensitive detection, i.e.,1-to-0 transition.
Cleared by software to specify level-sensitive detection, i.e., zero level.
1
These bits are not used in the control of Timer/Counter 0 and 1, but are used instead in the control and monitoring of the external INT0 and INT1 interrupt pins.
Timer/Counter 0 and 1 Data Registers
Each timer consists of two 8-bit registers. These can be used as
independent registers or combined into a single 16-bit register
depending on the timer mode configuration.
6
TR1
5
TF0
4
TR0
3
IE1
1
2
IT1
1
1
IE0
1
0
IT0
1
TH0 and TL0
Timer 0 high byte and low byte.
SFR Address = 8CH 8AH, respectively.
TH1 and TL1
Timer 1 high byte and low byte.
SFR Address = 8DH, 8BH, respectively.
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