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參數資料
| 型號： | ADUC842BCP32-5 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MicroConverter 12-Bit ADCs and DACs with Embedded High Speed 62-kB Flash MCU |
| 中文描述： | 8-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, QCC56 |
| 封裝： | 8 X 8 MM, LEAD FRAME, MO-220VLLD2, CSP-56 |
| 文件頁數： | 24/88頁 |
| 文件大小： | 903K |
| 代理商： | ADUC842BCP32-5 |
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ADuC841/ADuC842/ADuC843
ADCCON1—(ADC Control SFR 1)
The ADCCON1 register controls conversion and acquisition
times, hardware conversion modes, and power-down modes as
detailed below.
Rev. 0 | Page 24 of 88
SFR Address
SFR Power-On Default
Bit Addressable
Table 7. ADCCON1 SFR Bit Designations
Bit No.
Name
7
MD1
EFH
40H
No
Description
The mode bit selects the active operating mode of the ADC.
Set by the user to power up the ADC.
Cleared by the user to power down the ADC.
Set by the user to select an external reference.
Cleared by the user to use the internal reference.
The ADC clock divide bits (CK1, CK0) select the divide ratio for the PLL master clock (ADuC842/ADuC843) or the
external crystal (ADuC841) used to generate the ADC clock. To ensure correct ADC operation, the divider ratio
must be chosen to reduce the ADC clock to 8.38 MHz or lower. A typical ADC conversion requires 16 ADC clocks
plus the selected acquisition time.
The divider ratio is selected as follows:
CK1
0
0
1
1
1
2
The ADC acquisition select bits (AQ1, AQ0) select the time provided for the input track-and-hold amplifier to
acquire the input signal. An acquisition of three or more ADC clocks is recommended; clocks are as follows:
AQ1
0
0
1
1
1
4
The Timer 2 conversion bit (T2C) is set by the user to enable the Timer 2 overflow bit to be used as the ADC
conversion start trigger input.
The external trigger enable bit (EXC) is set by the user to allow the external Pin P3.5 (CONVST) to be used as the
active low convert start input. This input should be an active low pulse (minimum pulse width >100 ns) at the
required sample rate.
6
EXT_REF
5
4
CK1
CK0
CK0
0
1
0
MCLK Divider
32
4 (Do not use with a CD setting of 0)
8
3
2
AQ1
AQ0
AQ0
0
1
0
No. ADC Clks
1
2
3
1
T2C
0
EXC
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