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參數資料
| 型號： | ADUC842BCP32-5 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MicroConverter 12-Bit ADCs and DACs with Embedded High Speed 62-kB Flash MCU |
| 中文描述： | 8-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, QCC56 |
| 封裝： | 8 X 8 MM, LEAD FRAME, MO-220VLLD2, CSP-56 |
| 文件頁數： | 37/88頁 |
| 文件大小： | 903K |
| 代理商： | ADUC842BCP32-5 |
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ADuC841/ADuC842/ADuC843
CFG841
SFR Address
Power-On Default
Bit Addressable
Table 14. CFG841 SFR Bit Designations
Bit No.
Name
7
EXSP
Rev. 0 | Page 37 of 88
ADuC841 Config SFR
AFH
10H
1
No
Description
Extended SP Enable.
When set to 1 by the user, the stack rolls over from SPH/SP = 00FFH to 0100H.
When set to 0 by the user, the stack rolls over from SP = FFH to SP = 00H.
PWM Pin Out Selection.
Set to 1 by the user to select P3.4 and P3.3 as the PWM output pins.
Set to 0 by the user to select P2.6 and P2.7 as the PWM output pins.
DAC Output Buffer.
Set to 1 by the user to bypass the DAC output buffer.
Set to 0 by the user to enable the DAC output buffer.
Flash/EE Controller and PWM Clock Frequency Configuration Bits.
Frequency should be configured such that F
OSC
/Divide Factor = 32 kHz + 50%.
EPM2
EPM1
EPM0
Divide Factor
0 0 0 32
0 0 1
64
0 1 0 128
0 1 1 256
1
0 0 512
1 0 1 1024
Set to 1 by the user to move the SPI functionality of MISO, MOSI, and SCLOCK to P3.3, P3.4, and P3.5,
respectively.
Set to 0 by the user to leave the SPI functionality as usual on MISO, MOSI, and SCLOCK pins.
XRAM Enable Bit.
When set to 1 by the user, the internal XRAM is mapped into the lower two kBytes of the external address
space.
When set to 0 by the user, the internal XRAM is not accessible, and the external data memory is mapped into
the lower two kBytes of external data memory.
1
Note that the Flash/EE controller bits EPM2, EPM1, EPM0 are set to their correct values depending on the crystal frequency at power-up. The user should not modify
these bits so all instructions to the CFG841 register should use the ORL, XRL, or ANL instructions. Value of 10H is for 11.0592 MHz crystal.
6
PWPO
5
DBUF
4
EPM2
3
2
EPM1
EPM0
1
MSPI
0
XRAMEN
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