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參數資料
| 型號： | ADUC842BCP32-5 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MicroConverter 12-Bit ADCs and DACs with Embedded High Speed 62-kB Flash MCU |
| 中文描述： | 8-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, QCC56 |
| 封裝： | 8 X 8 MM, LEAD FRAME, MO-220VLLD2, CSP-56 |
| 文件頁數： | 36/88頁 |
| 文件大小： | 903K |
| 代理商： | ADUC842BCP32-5 |
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ADuC841/ADuC842/ADuC843
ADuC842/ADuC843 Configuration SFR (CFG842)
Rev. 0 | Page 36 of 88
The CFG842 SFR contains the necessary bits to configure the
internal XRAM, external clock select, PWM output selection,
DAC buffer, and the extended SP for both the ADuC842 and the
ADuC843. By default, it configures the user into 8051 mode, i.e.,
extended SP is disabled and internal XRAM is disabled. On the
ADuC841, this register is the CFG841 register and is described
on the next page.
Table 13. CFG842 SFR Bit Designations
Bit No.
Name
7
EXSP
CFG842
SFR Address
Power-On Default
Bit Addressable
ADuC842/ADuC843 Config SFR
AFH
00H
No
Description
Extended SP Enable.
When set to 1 by the user, the stack rolls over from SPH/SP = 00FFH to 0100H.
When set to 0 by the user, the stack rolls over from SP = FFH to SP = 00H.
PWM Pin Out Selection.
Set to 1 by the user to select P3.4 and P3.3 as the PWM output pins.
Set to 0 by the user to select P2.6 and P2.7 as the PWM output pins.
DAC Output Buffer.
Set to 1 by the user to bypass the DAC output buffer.
Set to 0 by the user to enable the DAC output buffer.
Set by the user to 1 to select an external clock input on P3.4.
Set by the user to 0 to use the internal PLL clock.
Reserved. This bit should always contain 0.
Reserved. This bit should always contain 0.
Set to 1 by the user to move the SPI functionality of MISO, MOSI, and SCLOCK to P3.3, P3.4, and P3.5,
respectively.
Set to 0 by the user to leave the SPI functionality as usual on MISO, MOSI, and SCLOCK pins.
XRAM Enable Bit.
When set to 1 by the user, the internal XRAM is mapped into the lower 2 kBytes of the external address
space.
When set to 0 by the user, the internal XRAM is not accessible, and the external data memory is
mapped into the lower 2 kBytes of external data memory.
6
PWPO
5
DBUF
4
EXTCLK
3
2
1
RSVD
RSVD
MSPI
0
XRAMEN
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