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參數資料
| 型號： | ADUC848BS32-3 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MicroConverter Multichannel 24-/16-Bit ADCs with Embedded 62 kB Flash and Single-Cycle MCU |
| 中文描述： | 8-BIT, FLASH, 12.58 MHz, MICROCONTROLLER, PQFP52 |
| 封裝： | 14 X 14 MM, PLASTIC, MO-112-AC-1, MQFP-52 |
| 文件頁數： | 60/108頁 |
| 文件大小： | 1109K |
| 代理商： | ADUC848BS32-3 |
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ADuC845/ADuC847/ADuC848
ON-CHIP PLL (PLLCON)
The ADuC845/ADuC847/ADuC848 are intended for use with a
32.768 kHz watch crystal. A PLL locks onto a multiple (384) of
this to provide a stable 12.582912 MHz clock for the system.
The core can operate at this frequency or at binary submultiples
of it to allow power saving when maximum core performance is
not required. The default core clock is the PLL clock divided by
8 or 1.572864 MHz. The ADC clocks are also derived from the
PLL clock, with the modulator rate being the same as the crystal
oscillator frequency. The control register for the PLL is called
PLLCON and is described as follows.
Rev. A | Page 60 of 108
The 5 V parts can be set to a maximum core frequency of
12.58 MHz (CD2...0 = 000) while at 3 V, the maximum core
clock rate is 6.29 MHz (CD2...0 = 001). The CD bits should not
be set to 000b on the 3 V parts.
The 3 V parts are limited to a core clock speed of 6.29 MHz
(CD = 1).
PLLCON PLL Control Register
SFR Address:
Power-On Default:
Bit Addressable:
D7H
53H
No
Table 39. PLLCON PLL Control Register
Bit No.
Name
7
OSC_PD
Description
Oscillator Power-Down Bit.
If low, the 32 kHz crystal oscillator continues running in power-down mode.
If high, the 32.768 kHz oscillator is powered down.
When this bit is low, the seconds counter continues to count in power-down mode and can interrupt the CPU
to exit power-down. The oscillator is always enabled in normal mode.
PLL Lock Bit. This is a read-only bit.
Set automatically at power-on to indicate that the PLL loop is correctly tracking the crystal clock. After power-
down, this bit can be polled to wait for the PLL to lock.
Cleared automatically at power-on to indicate that the PLL is not correctly tracking the crystal clock. This
might be due to the absence of a crystal clock or an external crystal at power-on. In this mode, the PLL output
can be 12.58 MHz ± 20%. After the part wakes up from power-down, user code can poll this bit to wait for the
PLL to lock. If LOCK = 0, the PLL is not locked.
Not Implemented. Write Don’t Care.
EA Status. Read-only bit. Reading this bit returns the state of the external EA pin latched at reset or power-on.
Fast Interrupt Response Bit.
Set by the user to enable the response to any interrupt to be executed at the fastest core clock frequency.
Cleared by the user to disable the fast interrupt response feature.
CPU (Core Clock) Divider Bits. This number determines the frequency at which the core operates.
CD2
CD1
CD0
Core Clock Frequency (MHz)
0
0
0
12.582912
0
0
1
6.291456 (Maximum core clock rate allowed on the 3 V parts)
0
1
0
3.145728
0
1
1
1.572864 (Default core frequency)
1
0
0
0.786432
1
0
1
0.393216
1
1
0
0.196608
1
1
1
0.098304
6
LOCK
5
4
3
–––
LTEA
FINT
2, 1, 0
CD2, CD1, CD0
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相關代理商/技術參數 |
參數描述 |
|---|---|
| ADUC848BS32-5 | 制造商:Analog Devices 功能描述:IC MICROCONTROLLER |
| ADUC848BS62-3 | 制造商:Rochester Electronics LLC 功能描述:8BIT CISC 62KB FLASH 12.85MHZ 3.3V 52MQFP - Bulk 制造商:Analog Devices 功能描述: |
| ADUC848BS62-5 | 制造商:Rochester Electronics LLC 功能描述:8BIT CISC 62KB FLASH 12.85MHZ 5V 52MQFP - Bulk 制造商:Analog Devices 功能描述:IC MICROCONTROLLER |
| ADUC848BS8-3 | 制造商:Analog Devices 功能描述: |
| ADUC848BS8-5 | 制造商:Analog Devices 功能描述:MCU 8-bit ADuC8xx 8052 CISC 62KB Flash 3.3V/5V 52-Pin MQFP 制造商:Analog Devices 功能描述:IC MICROCONTROLLER |
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