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參數資料
| 型號： | ADV202-SD-EB |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; No. of Contacts:13; Series:LJTP02R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:11; Circular Contact Gender:Socket; Circular Shell Style:Box Mount Receptacle |
| 中文描述： | JPEG2000的視頻編解碼器 |
| 文件頁數： | 10/40頁 |
| 文件大小： | 841K |
| 代理商： | ADV202-SD-EB |
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ADV202
DREQ/DACK DMA MODE—SINGLE FIFO READ OPERATION
Table 7.
Parameter
Description
DREQ
PULSE
DREQ Pulse Width
1
t
DREQ
DACK Assert to Subsequent DREQ Delay
t
RDSU
RD to DACK Setup
t
RD
DACK to Data Valid
t
HD
Data Hold
DACK
LO
DACK Assert Pulse Width
DACK
HI
DACK Deassert Pulse Width
t
RDHD
RD Hold after DACK Deassert
RDFSRQ
RD Assert to FSRQ Deassert (FIFO Empty)
t
DREQRTN
DACK to DREQ Deassert (DR × PULS = 0)
Rev. 0 | Page 10 of 40
Min
1
2.5
0
Typ
Max
15
3.5 × JCLK + 7.5 ns
Unit
JCLK cycles
2
JCLK cycles
ns
2.5
11
ns
1.5
2
2
0
ns
JCLK cycles
JCLK cycles
ns
1.5
2.5
2.5 × JCLK + 7.5 ns
3.5 × JCLK + 7.5 ns
JCLK cycles
JCLK cycles
1
Applies to assigned DMA channel, if EDMOD0 or EDMOD1 <14:11> is programmed to a nonzero value.
2
For a definition of JCLK, see the
section.
PLL
0
RD
DACK
DREQ
HDATA
0
1
2
t
RD
t
HD
DREQ
PULSE
t
DREQ
t
RDSU
t
RDHD
DACK
HI
DACK
LO
Figure 9. Single Read for DREQ/DACK DMA Mode for Assigned DMA Channel
(EDMOD0/EDMOD1 <14:11> NOT Programmed to a Value of 0000)
0
RD
DACK
DREQ
HDATA
0
1
2
t
RD
t
HD
t
DREQRTN
t
RDSU
t
RDHD
DACK
HI
DACK
LO
Figure 10. Single Read forDREQ/DACK DMA Mode for Assigned DMA Channel
(EDMOD0/EDMOD1 <14:11> Programmed to a Value of 0000)
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