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參數資料
| 型號： | ADV202-SD-EB |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; No. of Contacts:13; Series:LJTP02R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:11; Circular Contact Gender:Socket; Circular Shell Style:Box Mount Receptacle |
| 中文描述： | JPEG2000的視頻編解碼器 |
| 文件頁數： | 12/40頁 |
| 文件大小： | 841K |
| 代理商： | ADV202-SD-EB |
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ADV202
EXTERNAL DMA MODE—FIFO WRITE, BURST MODE
Table 8.
Parameter
Desription
DREQ
PULSE
DREQ Pulse Width
1
t
DREQRTN
DACK to DREQ Deassert (DR × Pulse = 0)
t
DACKSU
DACK to WE Setup
t
SU
Data Setup
t
HD
Data Hold
WE
LO
WE Assert Pulse Width
WE
HI
WE Deassert Pulse Width
t
DREQWAIT
DACK Deassert to Next DREQ
Rev. 0 | Page 12 of 40
Min
1
2.5
Typ
Max
15
3.5 × JCLK + 7.5 ns
Unit
JCLK cycles
2
JCLK cycles
0
2.5
2
1.5
1.5
2.5
4.5 × JCLK + 7.5 ns
3
ns
ns
ns
JCLK cycles
JCLK cycles
JCLK cycles
1
Applies to assigned DMA channel, if EDMOD0 or EDMOD1 <14:11> is programmed to a value that is NOT 0. Pulse width depends on the value programmed.
2
For a definition of JCLK, see the
section.
PLL
3
If sufficient space is available in FIFO.
0
DREQ
DACK
WE
HDATA
WE
HI
WE
LO
t
DACKSU
t
HD
t
SU
0
1
13
14
15
t
DREQWAIT
DREQ
PULSE
Figure 13. Burst Write Cycle forDREQ/DMA Mode for Assigned DMA Channel
(EDMOD0/EDMOD1 <14:11> NOT Programmed to a Value of 0000)
0
DREQ
DACK
WE
HDATA
WE
HI
WE
LO
t
DACKSU
t
HD
t
SU
0
1
13
14
15
t
DREQWAIT
t
DREQRTN
Figure 14. Burst Write Cycle for DREQ/DMA Mode for Assigned DMA Channel
(EDMOD0/EDMOD1 <14:11> Programmed to a Value of 0000)
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