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參數資料
| 型號： | ADV202-SD-EB |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; No. of Contacts:13; Series:LJTP02R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:11; Circular Contact Gender:Socket; Circular Shell Style:Box Mount Receptacle |
| 中文描述： | JPEG2000的視頻編解碼器 |
| 文件頁數： | 13/40頁 |
| 文件大小： | 841K |
| 代理商： | ADV202-SD-EB |
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ADV202
Rev. 0 | Page 13 of 40
0
DREQ
DACK
WEFB
HDATA
WE
HI
WE
LO
t
DACKSU
t
HD
t
SU
0
1
13
14
15
t
DREQWAIT
t
DREQRTN
Figure 15. Burst Write Cycle for Fly-By DMA Mode
(DREQ Pulse Width Is Programmable)
EXTERNAL DMA MODE—FIFO READ, BURST MODE
Table 9.
Parameter
Description
DREQ
PULSE
DREQ Pulse Width
1
t
DREQRTN
DACK to DREQ Deassert (DR × PULS = 0)
t
DACKSU
DACK to RD Setup
t
RD
DACK to Data Valid
t
HD
Data Hold
RD
LO
RD Assert Pulse Width
RD
HI
RD Deassert Pulse Width
t
DREQWAIT
DACK Deassert to Next DREQ
Min
1
2.5
Typ
Max
15
3.5 × JCLK + 7.5 ns
Unit
JCLK cycles
2
JCLK cycles
0
ns
2.5
2.5
1.5
1.5
2.5
9.7
3.5 × JCLK + 7.5 ns
3
ns
ns
JCLK cycles
JCLK cycles
JCLK cycles
1
Applies to assigned DMA channel, if EDMOD0 or EDMOD1 <14:11> is programmed to a value that is not 0. Pulse width depends on the value programmed.
2
For a definition of JCLK, see the
section.
PLL
3
If sufficient data is available in FIFO.
0
DREQ
DACK
RD
HDATA
RD
HI
RD
LO
t
DACKSU
t
HD
0
1
13
14
15
t
DREQWAIT
DREQ
PULSE
t
RD
Figure 16. Burst Read Cycle for DREQ/DACK DMA Mode for Assigned DMA Channel
(EMOD0/EDMOD1 <14:11> NOT Programmed to a Value of 0
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