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參數(shù)資料
| 型號： | ADV202-SD-EB |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; No. of Contacts:13; Series:LJTP02R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:11; Circular Contact Gender:Socket; Circular Shell Style:Box Mount Receptacle |
| 中文描述： | JPEG2000的視頻編解碼器 |
| 文件頁數(shù)： | 8/40頁 |
| 文件大小： | 841K |
| 代理商： | ADV202-SD-EB |
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ADV202
DREQ/DACK DMA MODE—SINGLE FIFO WRITE OPERATION
Table 6.
Parameter
Description
DREQ
PULSE1
DREQ Pulse Width
t
DREQ
DACK Assert to Subsequent DREQ Delay
t
WESU
WE to DACK Setup
t
SU
Data to DACK Deassert Setup
t
HD
Data to DACK Deassert Hold
DACK
LO
DACK Assert Pulse Width
DACK
HI
DACK Deassert Pulse Width
t
WEHD
WE Hold after DACK Deassert
WFSRQ
WE Assert to FSRQ Deassert (FIFO Full)
t
DREQRTN
DACK to DREQ Deassert (DR × PULS = 0)
Rev. 0 | Page 8 of 40
Min
1
2.5
Typ
Max
15
3.5 × JCLK + 7.5 ns
Unit
JCLK cycles
2
JCLK cycles
0
2
2
2
2
0
1.5
2.5
2.5 × JCLK + 7.5 ns
3.5 × JCLK + 7.5 ns
ns
ns
ns
JCLK cycles
JCLK cycles
ns
JCLK cycles
JCLK cycles
1
Applies to assigned DMA channel, if EDMOD0 or EDMOD1 <14:11> is programmed to a value that is not 0. Pulse width depends on the value programmed.
2
For a definition of JCLK, see the PLL section.
0
WE
DACK
DREQ
HDATA
3
2
1
0
DREQ
PULSE
t
DREQ
DACK
HI
DACK
LO
t
WESU
t
SU
t
HD
t
WEHD
Figure 5. Single Write for DREQ/DACK DMA Mode for Assigned DMA Channel
(EDMOD0/EDMOD1 <14:11> NOT Programmed to a Value of 0000)
0
WE
DACK
DREQ
HDATA
0
1
2
t
DREQRTN
DACK
HI
DACK
LO
t
WESU
t
SU
t
HD
t
WEHD
Figure 6. Single Write for DREQ/DACK DMA Mode for Assigned DMA Channel
(EDMOD0/EDMOD1 <14:11> Programmed to a Value of 0000)
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| ADV202XBBCZ-150 | 制造商:Analog Devices 功能描述:JPEG 2000 CODEC CONVERTER - Trays |
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