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參數(shù)資料
| 型號(hào)： | ADV601LC |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 視頻Codec |
| 英文描述： | Ultralow Cost Video Codec |
| 中文描述： | 超低成本視頻編解碼器 |
| 文件頁(yè)數(shù)： | 11/52頁(yè) |
| 文件大小： | 606K |
| 代理商： | ADV601LC |
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ADV601
–11–
REV. 0
[4]
FIFO Error,
FIFOERR
. This condition indicates that the host has been unable to keep up with the ADV601’s compressed
data supply or demand requirements. If this condition occurs during encode, the data stream will not be corrupted until
MERR indicates that the DRAM is also overflowed. If this condition occurs during decode, the video output will be
corrupted. If the system overflows the FIFO (disregarding a FIFOSTP condition) with too many writes in decode mode,
FIFOERR is asserted. This read only status bit indicates the following:
0
No FIFO Error condition,
reset value
(FIFO_ERR pin LO)
1
FIFO overflow (encode) or underflow (decode) (FIFO_ERR pin HI)
FIFO Stop,
FIFOSTP
. This condition indicates that the FIFO is full in decode mode and empty in encode mode.
In decode mode only, FIFOSTP status actually behaves more conservatively than this. In decode mode, even when
FIFOSTP is indicated, there are still 32 empty Dwords available in the FIFO and 32 more Dword writes can safely
be performed. This status bit indicates the following:
0
No FIFO Stop condition,
reset value
(FIFO_STP pin LO)
1
FIFO empty (encode) or full (decode) (FIFO_STP pin HI)
Memory Error,
MERR
. This condition indicates that an error has occurred at the DRAM memory interface. This condition can
be caused by a defective DRAM, the inability of the Host to keep up with the ADV601 compressed data stream, or bit errors in
the data stream. Note that the ADV601 recovers from this condition without host intervention.
0
No memory error condition,
reset value
1
Memory error
Reserved (always read/write zero)
Interrupt Enable on CCIRER,
IE_CCIRER
. This mask bit selects the following:
0
Disable CCIR-656 data error interrupt,
reset value
1
Enable interrupt on error in CCIR-656 data
Interrupt Enable on STATR,
IE_STATR
. This mask bit selects the following:
0
Disable Statistics Ready interrupt,
reset value
1
Enable interrupt on Statistics Ready
Interrupt Enable on LCODE,
IE_LCODE
. This mask bit selects the following:
0
Disable Last Code Read interrupt,
reset value
1
Enable interrupt on Last Code Read from FIFO
Interrupt Enable on FIFOSRQ,
IE_FIFOSRQ
. This mask bit selects the following:
0
Disable FIFO Service Request interrupt,
reset value
1
Enable interrupt on FIFO Service Request
Interrupt Enable on FIFOERR,
IE_FIFOERR
. This mask bit selects the following:
0
Disable FIFO Stop interrupt,
reset value
1
Enable interrupt on FIFO Stop
Interrupt Enable on FIFOSTP,
IE_FIFOSTP
. This mask bit selects the following:
0
Disable FIFO Error interrupt,
reset value
1
Enable interrupt on FIFO Error
Interrupt Enable on MERR,
IE_MERR
. This mask bit selects the following:
0
Disable memory error interrupt,
reset value
1
Enable interrupt on memory error
Reserved (always read/write zero)
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]
Mode Control Register
Indirect (Write Only) Register Index 0x00
This register holds configuration data for the ADV601’s video interface format and controls several other video interface features.
For more information on formats and modes, see the Video Interface section. Bits in this register have the following functions:
[3:0]
Video Interface Format,
VIF[3:0]
. These bits select the interface format. Valid settings include the following (all
other values are reserved):
0x0
CCIR-656
0x2
MLTPX (Philips)
0x3
Philips,
reset value
0x8
Gray Scale
[4]
VCLK Output Divided by two,
VCLK2
. This bit controls the following:
0
Do not divide VCLK output (VCLKO = VCLK),
reset value
1
Divide VCLK output by two (VCLKO = VCLK/2)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV601LCERAG1266B-0.5 | 制造商:Analog Devices 功能描述: |
| ADV601LCJST | 制造商:Analog Devices 功能描述:Ultralow Cost Video Codec 120-Pin LQFP 制造商:Analog Devices 功能描述:IC VIDEO CODEC |
| ADV601LCJSTRL | 制造商:Analog Devices 功能描述:Ultralow Cost Video Codec 120-Pin LQFP T/R |
| ADV601LCJSTZ | 功能描述:IC CODEC VIDEO DSP/SRL 120LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標(biāo)準(zhǔn) ADC / DAC (db):81.5 / 88 動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR) |
| ADV601LCJSTZRL | 功能描述:IC CODEC VIDEO DSP/SRL 120LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標(biāo)準(zhǔn) ADC / DAC (db):81.5 / 88 動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR) |
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