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參數資料
| 型號： | ADV7180BCPZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顏色信號轉換 |
| 英文描述： | 10-Bit, 4 x Oversampling SDTV Video Decoder |
| 中文描述： | COLOR SIGNAL DECODER, QCC40 |
| 封裝： | 6 X 6 MM, ROHS COMPLIANT, MO-220VJJD-2, LFCSP-40 |
| 文件頁數： | 57/112頁 |
| 文件大小： | 1320K |
| 代理商： | ADV7180BCPZ |
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ADV7180
I
2
C Interface
Dedicated I
2
C readback registers are available for CCAP,
CGMS, WSS, Gemstar, VPS, PDC/UTC, and VITC. Because
teletext is a high data rate standard, data extraction is supported
only through the ancillary data packet. The details of these
registers and their access procedure are described next.
User Interface for I
2
C Readback Registers
The VDP decodes all enabled VBI data standards in real time.
Because the I
2
C access speed is much lower than the decoded
rate, when the registers are accessed, they may be updated with
data from the next line. To avoid this, VDP has a self-clearing
CLEAR bit and an AVAILABLE status bit accompanying all
I
2
C readback registers.
The user has to clear the I
2
C readback register by writing a high
to the CLEAR bit. This resets the state of the AVAILABLE bit to
low and indicates that the data in the associated readback
registers is not valid. After the VDP decodes the next line of the
corresponding VBI data, the decoded data is placed into the I
2
C
readback register and the AVAILABLE bit is set to high to
indicate that valid data is now available.
Though the VDP decodes this VBI data in subsequent lines if
present, the decoded data is not updated to the readback
registers until the CLEAR bit is set high again. However, this
data is available through the 656 ancillary data packets.
The CLEAR and AVAILABLE bits are in the VDP_CLEAR
(0x78, User Sub Map, write only) and VDP_STATUS (0x78,
User Sub Map, read only) registers.
Example I
2
C Readback Procedure
The following tasks have to be performed to read one packet
(line) of PDC data from the decoder:
1.
Write 10 to I
2
C_GS_VPS_PDC_UTC[1:0] (0x9C, User Sub
Map) to specify that PDC data has to be updated to I
2
C
registers.
2.
Write high to the GS_PDC_VPS_UTC_CLEAR bit (0x78,
User Sub Map) to enable I
2
C register updating.
3.
Poll the GS_PDC_VPS_UTC_AVL bit (0x78, User Sub
Map) going high to check the availability of the PDC
packets.
4.
Read the data bytes from the PDC I
2
C registers. Repeat
Step 1 to Step 3 to read another line or packet of data.
To read a packet of CCAP, CGMS, or WSS data, only Step 1 to
Step 3 are required because they have dedicated registers.
VDP—Content-Based Data Update
For certain standards like WSS, CGMS, Gemstar, PDC, UTC,
and VPS, the information content in the signal transmitted
remains the same over numerous lines, and the user may want
Rev. A | Page 57 of 112
to be notified only when there is a change in the information
content or loss of the information content. The user needs to
enable content-based updating for the required standard
through the GS_VPS_PDC_UTC_CB_CHANGE and
WSS_CGMS_CB_CHANGE bits. Therefore, the AVAILABLE
bit shows the availability of that standard only when its content
has changed.
Content-based updating also applies to lines with lost data.
Therefore, for standards like VPS, Gemstar, CGMS, and WSS, if no
data arrives in the next four lines programmed, the corresponding
AVAILABLE bit in the VDP_STATUS register is set high and
the content in the I
2
C registers for that standard is set to 0. The
user has to write high to the corresponding CLEAR bit so that
when a valid line is decoded after some time, the decoded results
are available in the I
2
C registers, with the AVAILABLE status
bit set high.
If content-based updating is enabled, the AVAILABLE bit is set
high (assuming the CLEAR bit was written) in the following cases:
The data contents have changed.
Data was being decoded and four lines with no data have
been detected.
No data was being decoded and new data is now being
decoded.
GS_VPS_PDC_UTC_CB_CHANGE, Enable Content-
Based Updating for Gemstar/VPS/PDC/UTC,
Address 0x9C [5], User Sub Map
0—Disables content-based updating.
1 (default)—Enables content-based updating.
WSS_CGMS_CB_CHANGE, Enable Content-Based
Updating for WSS/CGMS, Address 0x9C [4],
User Sub Map
0—Disables content-based updating.
1 (default)—Enables content-based updating.
VDP—Interrupt-Based Reading of VDP I
2
C Registers
Some VDP status bits are also linked to the interrupt request
controller so that the user does not have to poll the AVAILABLE
status bit. The user can configure the video decoder to trigger
an interrupt request on the INTRQ pin in response to the valid
data available in I
2
C registers. This function is available for the
following data types:
CGMS or WSS:
The user can select either triggering
an interrupt request each time sliced data is available
or triggering an interrupt request only when the
sliced data has changed. Selection is made via the
WSS_CGMS_CB_CHANGE bit.
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| ADV7180BSTZ | 10-Bit, 4 x Oversampling SDTV Video Decoder |
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相關代理商/技術參數 |
參數描述 |
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| ADV7180BCPZ | 制造商:Analog Devices 功能描述:IC VIDEO DECODER 10BIT 57.27MSPS LFCSP40 |
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| ADV7180BSTZ | 功能描述:IC VIDEO DECODER SDTV 64-LQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 標準包裝:250 系列:- 類型:電平移位器 應用:LCD 電視機/監控器 安裝類型:表面貼裝 封裝/外殼:28-WFQFN 裸露焊盤 供應商設備封裝:28-WQFN（4x4）裸露焊盤 包裝:帶卷 (TR) 其它名稱:296-32523-2TPS65198RUYT-ND |
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