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參數資料
| 型號： | ADV7181B |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Multiformat SDTV Video Decoder |
| 中文描述： | 標清多格式視頻解碼器 |
| 文件頁數： | 29/96頁 |
| 文件大小： | 873K |
| 代理商： | ADV7181B |
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ADV7181B
CSFM[2:0] C Shaping Filter Mode, Address 0x17 [7]
Rev. 0 | Page 29 of 96
The C shaping filter mode bits allow the user to select from a
range of low-pass filters for the chrominance signal. When
switched in automatic mode, the widest filter is selected based
on the video standard/format and user choice (see settings 000
and 001 in Table 30).
Table 30. CSFM Function
CSFM[2:0]
Description
000 (default)
Autoselect 1.5 MHz bandwidth
001
Autoselect 2.17 MHz bandwidth
010
SH1
011
SH2
100
SH3
101
SH4
110
SH5
111
Wideband mode
0
–10
–20
–30
–40
–50
–60
0
5
4
3
2
1
6
0
FREQUENCY (MHz)
v740a COMBINED C RESAMPLER
A
Figure 15. Chroma Shaping Filter Responses
Figure 15 shows the responses of SH1 (narrowest) to SH5
(widest) in addition to the wideband mode (in red).
GAIN OPERATION
The gain control within the ADV7181B is done on a purely
digital basis. The input ADCs support a 9-bit range, mapped
into a 1.6 V analog voltage range. Gain correction takes place
after the digitization in the form of a digital multiplier.
Advantages of this architecture over the commonly used PGA
(programmable gain amplifier) before the ADC include the fact
that the gain is now completely independent of supply,
temperature, and process variations.
As shown in Figure 16, the ADV7181B can decode a video
signal as long as it fits into the ADC window. The components
to this are the amplitude of the input signal and the dc level it
resides on. The dc level is set by the clamping circuitry (see the
Clamp Operation section).
If the amplitude of the analog video signal is too high, clipping
may occur, resulting in visual artifacts. The analog input range
of the ADC, together with the clamp level, determines the
maximum supported amplitude of the video signal.
The minimum supported amplitude of the input video is
determined by the ADV7181B’s ability to retrieve horizontal
and vertical timing and to lock to the color burst, if present.
There are separate gain control units for luma and chroma data.
Both can operate independently of each other. The chroma unit,
however, can also take its gain value from the luma path.
The possible AGC modes are summarized in Table 31.
It is possible to freeze the automatic gain control loops. This
causes the loops to stop updating and the AGC determined gain
at the time of the freeze to stay active until the loop is either
unfrozen or the gain mode of operation is changed.
The currently active gain from any of the modes can be read
back. Refer to the description of the dual-function manual gain
registers, LG[11:0] Luma Gain and CG[11:0] Chroma Gain, in
the Luma Gain and the Chroma Gain sections.
0
ANALOG VOLTAGE
RANGE SUPPORTED BY ADC (1.6V RANGE FOR ADV7181B)
DATA
PRE-
PROCESSOR
(DPP)
ADC
SDP
(GAIN SELECTION ONLY)
MAXIMUM
VOLTAGE
MINIMUM
VOLTAGE
CLAMP
LEVEL
GAIN
CONTROL
Figure 16. Gain Control Overview
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| ADV7181BBSTZ | Multiformat SDTV Video Decoder |
| ADV7181BCP | Multiformat SDTV Video Decoder |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| ADV7181BBCPZ | 制造商:Analog Devices 功能描述:Video Decoder 3ADC 9-Bit 64-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:ADV718XB DECODER FAMILY UPDATES - Bulk 制造商:Analog Devices 功能描述:IC VIDEO ENCODER |
| ADV7181BBSTZ | 制造商:Analog Devices 功能描述:Video Decoder 3ADC 9-Bit 64-Pin LQFP 制造商:Analog Devices 功能描述:IC VIDEO ENCODER |
| ADV7181BCP | 制造商:Analog Devices 功能描述:Video Decoder 3ADC 9-Bit 64-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:10BIT NTSC/PAL/SECAM VIDEO DECODER I.C. - Bulk |
| ADV7181BCPZ | 制造商:Analog Devices 功能描述: |
| ADV7181BST | 制造商:Analog Devices 功能描述:Video Decoder 3ADC 9-Bit 64-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:9-BIT BIT NTSC/PAL/SECAM VIDEO DECODER - Bulk 制造商:Analog Devices 功能描述:IC VIDEO ENCODER |
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