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參數資料
| 型號： | ADV7181B |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Multiformat SDTV Video Decoder |
| 中文描述： | 標清多格式視頻解碼器 |
| 文件頁數： | 44/96頁 |
| 文件大小： | 873K |
| 代理商： | ADV7181B |
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ADV7181B
Rev. 0 | Page 44 of 96
0
ADVANCE BEGIN OF
VSYNC BY PVBEG[4:0]
DELAY BEGIN OF
VSYNC BY PVBEG[4:0]
VSYNC BEGIN
PVBEGSIGN
ODD FIELD
0
1
NO
YES
PVBEGDELO
VSBHO
ADDITIONAL
DELAY BY
1 LINE
ADVANCE BY
0.5 LINE
1
0
1
0
PVBEGDELE
VSBHE
ADDITIONAL
DELAY BY
1 LINE
ADVANCE BY
0.5 LINE
1
0
1
0
NOT VALID FOR USER
PROGRAMMING
Figure 27. PAL VSync Begin
PVBEGDELO PAL VSync Begin Delay on Odd Field,
Address 0xE8 [7]
When PVBEGDELO is 0 (default), there is no delay.
Setting PVBEGDELO to 1 delays VSync going high on an odd
field by a line relative to PVBEG.
PVBEGDELE PAL VSync Begin Delay on Even Field,
Address 0xE8 [6]
When PVBEGDELE is 0, there is no delay.
Setting PVBEGDELE to 1 (default) delays VSync going high on
an even field by a line relative to PVBEG.
PVBEGSIGN PAL VSync Begin Sign, Address 0xE8 [5]
Setting PVBEGSIGN to 0 delays the beginning of VSync. Set for
user manual programming.
Setting PVBEGSIGN to 1(default) advances the beginning of
VSync. Not recommended for user programming.
PVBEG[4:0] PAL VSync Begin, Address 0xE8 [4:0]
The default value of PVBEG is 00101, indicating the PAL VSync
begin position.
For all NTSC/PAL VSync timing controls, both the V bit in the
AV code and the VSync on the VS pin are modified.
0
ADVANCE END OF
VSYNC BY PVEND[4:0]
DELAY END OF VSYNC
BY PVEND[4:0]
VSYNC END
PVENDSIGN
ODD FIELD
0
1
NO
YES
PVENDDELO
VSEHO
ADDITIONAL
DELAY BY
1 LINE
ADVANCE BY
0.5 LINE
1
0
1
0
PVENDDELE
VSEHE
ADDITIONAL
DELAY BY
1 LINE
ADVANCE BY
0.5 LINE
1
0
1
0
NOT VALID FOR USER
PROGRAMMING
Figure 28. PAL VSync End
PVENDDELO PAL VSync End Delay on Odd Field,
Address 0xE9,[7]
When PVENDDELO is 0 (default), there is no delay.
Setting PVENDDELO to 1 delays VSync going low on an odd
field by a line relative to PVEND.
PVENDDELE PAL VSync End Delay on Even Field,
Address 0xE9,[6]
When PVENDDELE is 0 (default), there is no delay.
Setting PVENDDELE to 1 delays VSync going low on an even
field by a line relative to PVEND.
相關PDF資料 |
PDF描述 |
|---|---|
| ADV7181BBCPZ | Multiformat SDTV Video Decoder |
| ADV7181BBSTZ | Multiformat SDTV Video Decoder |
| ADV7181BCP | Multiformat SDTV Video Decoder |
| ADV7181BST | Multiformat SDTV Video Decoder |
| ADV7183B | Multiformat SDTV Video Decoder |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ADV7181BBCPZ | 制造商:Analog Devices 功能描述:Video Decoder 3ADC 9-Bit 64-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:ADV718XB DECODER FAMILY UPDATES - Bulk 制造商:Analog Devices 功能描述:IC VIDEO ENCODER |
| ADV7181BBSTZ | 制造商:Analog Devices 功能描述:Video Decoder 3ADC 9-Bit 64-Pin LQFP 制造商:Analog Devices 功能描述:IC VIDEO ENCODER |
| ADV7181BCP | 制造商:Analog Devices 功能描述:Video Decoder 3ADC 9-Bit 64-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:10BIT NTSC/PAL/SECAM VIDEO DECODER I.C. - Bulk |
| ADV7181BCPZ | 制造商:Analog Devices 功能描述: |
| ADV7181BST | 制造商:Analog Devices 功能描述:Video Decoder 3ADC 9-Bit 64-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:9-BIT BIT NTSC/PAL/SECAM VIDEO DECODER - Bulk 制造商:Analog Devices 功能描述:IC VIDEO ENCODER |
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