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參數資料
| 型號： | ADV7183B |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Multiformat SDTV Video Decoder |
| 中文描述： | 標清多格式視頻解碼器 |
| 文件頁數： | 58/100頁 |
| 文件大小： | 844K |
| 代理商： | ADV7183B |
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ADV7183B
Interrupt Request Output Operation
When an interrupt event occurs, the interrupt pin INTRQ
goes low with a programmable duration given by
INTRQ_DUR_SEL[1:0]
Rev. B | Page 58 of 100
INTRQ_DURSEL[1:0], Interrupt Duration Select
Address 0x40 (Interrupt Space)[7:6]
Table 76. INTRQ_DUR_SEL
INTRQ_DURSEL[1:0]
Description
00 (default)
3 Xtal periods
01
15 Xtal periods
10
63 Xtal periods
11
Active until cleared
When the active until cleared interrupt duration is selected and
the event that caused the interrupt is no longer in force, the
interrupt persists until it is masked or cleared.
For example, if the ADV7183B loses lock, an interrupt is
generated and INTRQ pin goes low. If the ADV7183B returns
to the locked state, INTRQ continues to drive low until the
SD_LOCK bit is either masked or cleared.
Interrupt Drive Level
The ADV7183B resets with open drain enabled and all
interrupts masked off. Therefore, INTRQ is in a high
impedance state after reset. 01 or 10 has to be written to
INTRQ_OP_SEL[1:0] for a logic level to be driven out from the
INTRQ pin.
It is also possible to write to a register in the ADV7183B that
manually asserts the INTRQ pin. This bit is MPU_STIM_INTRQ.
INTRQ_OP_SEL[1:0], Interrupt Duration Select
Address 0x40 (Interrupt Space)[1:0]
Table 77. INTRQ_OP_SEL
INTRQ_OP_SEL[1:0]
Description
00 (default)
Open drain
01
Drive low when active
10
11
Reserved
Multiple Interrupt Events
If Interrupt Event 1 occurs and then Interrupt Event 2 occurs
before the system controller has cleared or masked Interrupt
Event 1, the ADV7183B will not generate a second interrupt
signal. The system controller should check all unmasked
interrupt status bits, as more than one can be active.
Drive high when active
Macrovision Interrupt Selection Bits
The user can select between pseudo sync pulse and color stripe
detection as shown in this section.
MV_INTRQ_SEL[1:0], Macrovision Interrupt Selection
Bits Address 0x40 (Interrupt Space)[5:4]
Table 78. MV_INTRQ_SEL
MV_INTRQ_SEL[1:0]
Description
00
Reserved
01 (default)
Pseudo sync only
10
11
Either pseudo sync or color stripe
Color stripe only
Additional information relating to the interrupt system is
detailed in
255H
Table 84.
相關PDF資料 |
PDF描述 |
|---|---|
| ADV7183BBSTZ | Multiformat SDTV Video Decoder |
| ADV7183BKSTZ | Multiformat SDTV Video Decoder |
| ADV7183KST | Advanced Video Decoder with 10-Bit ADC and Component Input Support |
| AD7183 | Advanced Video Decoder with 10-Bit ADC and Component Input Support |
| ADV7185 | Professional NTSC/PAL Video Decoder with 10-Bit CCIR656 Output |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ADV7183BBSTZ | 功能描述:IC VIDEO DECODER NTSC 80-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉換器 系列:- 產品變化通告:Development Systems Discontinuation 26/Apr/2011 標準包裝:1 系列:- 類型:編碼器 應用:DVB-S.2 系統 電壓 - 電源，模擬:- 電壓 - 電源，數字:- 安裝類型:- 封裝/外殼:模塊 供應商設備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| ADV7183BKST | 制造商:Analog Devices 功能描述:MULTIFORMAT SDTV VID DECODER 80LQFP - Bulk |
| ADV7183BKSTZ | 功能描述:IC VIDEO DECODER NTSC 80-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉換器 系列:- 產品變化通告:Development Systems Discontinuation 26/Apr/2011 標準包裝:1 系列:- 類型:編碼器 應用:DVB-S.2 系統 電壓 - 電源，模擬:- 電壓 - 電源，數字:- 安裝類型:- 封裝/外殼:模塊 供應商設備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| ADV7183KST | 制造商:Analog Devices 功能描述:Video Decoder 2ADC 10-Bit 80-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:VIDEO DECODER I.C. - Bulk |
| ADV7184 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat SDTV Video Decoder with Fast Switch Overlay Support |
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