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參數資料
| 型號： | ADV7183B |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Multiformat SDTV Video Decoder |
| 中文描述： | 標清多格式視頻解碼器 |
| 文件頁數： | 59/100頁 |
| 文件大小： | 844K |
| 代理商： | ADV7183B |
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ADV7183B
PIXEL PORT CONFIGURATION
The ADV7183B has a very flexible pixel port that can be confi-
gured in a variety of formats to accommodate downstream ICs.
256H
Table 79 and
257H
Table 80 summarize the various functions that the
ADV7183B’s pins can have in different modes of operation.
Rev. B | Page 59 of 100
The ordering of components (for example, Cr versus Cb,
CHA/B/C) can be changed. Refer to the section.
258H
Table 79
indicates the default positions for the Cr/Cb components.
OF_SEL[3:0] Output Format Selection, Address 0x03[5:2]
The modes in which the ADV7183B pixel port can be onfigured
are under the control of OF_SEL[3:0]. See
259H
Table 80 for details.
The default LLC frequency output on the LLC1 pin is
approximately 27 MHz. For modes that operate with a nominal
data rate of 13.5 MHz (0001, 0010), the clock frequency on the
LLC1 pin stays at the higher rate of 27 MHz. For information
on outputting the nominal 13.5 MHz clock on the LLC1 pin, see
the
260H
PAD_SEL[2:0], Address 0x8F[6:4] section.
Table 79. P15 to P0 Output/Input Pin Mapping
Format, and Mode
Video Out, 8-Bit, 4:2:2
Video Out, 16-Bit, 4:2:2
SWPC Swap Pixel Cr/Cb, Address 0x27[7]
This bit allows Cr and Cb samples to be swapped.
When SWPC is 0 (default), no swapping is allowed.
When SWPC is 1, the Cr and Cb values can be swapped.
PAD_SEL[2:0], Address 0x8F[6:4]
This I
2
C write allows the user to select between the LLC1
(nominally at 27 MHz) and LLC2 (nominally at 13.5 MHz).
The LLC2 signal is useful for LLC2-compatible wide bus
(16-bit) output modes. See the
261H
OF_SEL[3:0] Output Format
Selection, Address 0x03[5:2] section for additional information.
The LLC2 signal and data on the data bus are synchronized. By
default, the rising edge of LLC1/LLC2 is aligned with the Y
data; the falling edge occurs when the data bus holds C data.
The polarity of the clock, and therefore the Y/C assignments to
the clock edges, can be altered by using the Polarity LLC pin.
When LLC_PAD_SEL[2:0] is 000 (default), the output is
nominally 27 MHz LLC on the LLC1 pin.
When LLC_PAD_SEL[2:0] is 101, the output is nominally
13.5 MHz LLC on the LLC1 pin.
Data Port Pins P[15:0]
10
9
15
14
13
12
11
8
7
6
5
4
3
2
1
0
YCrCb[7:0] OUT
Y[7:0] OUT
CrCb[7:0] OUT
Table 80. Standard Definition Pixel Port Modes
OF_SEL[3:0]
0010
0011 (default)
0110-1111
Format
16-bit @ LLC2 4:2:2
8-bit @ LLC1 4:2:2 (default)
Reserved
P[15: 0]
P[15:8]
Y[7:0]
YCrCb[7:0] (default)
P[7: 0]
CrCb[7:0]
Three-state
Reserved. Do not use.
相關PDF資料 |
PDF描述 |
|---|---|
| ADV7183BBSTZ | Multiformat SDTV Video Decoder |
| ADV7183BKSTZ | Multiformat SDTV Video Decoder |
| ADV7183KST | Advanced Video Decoder with 10-Bit ADC and Component Input Support |
| AD7183 | Advanced Video Decoder with 10-Bit ADC and Component Input Support |
| ADV7185 | Professional NTSC/PAL Video Decoder with 10-Bit CCIR656 Output |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ADV7183BBSTZ | 功能描述:IC VIDEO DECODER NTSC 80-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉換器 系列:- 產品變化通告:Development Systems Discontinuation 26/Apr/2011 標準包裝:1 系列:- 類型:編碼器 應用:DVB-S.2 系統 電壓 - 電源，模擬:- 電壓 - 電源，數字:- 安裝類型:- 封裝/外殼:模塊 供應商設備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| ADV7183BKST | 制造商:Analog Devices 功能描述:MULTIFORMAT SDTV VID DECODER 80LQFP - Bulk |
| ADV7183BKSTZ | 功能描述:IC VIDEO DECODER NTSC 80-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉換器 系列:- 產品變化通告:Development Systems Discontinuation 26/Apr/2011 標準包裝:1 系列:- 類型:編碼器 應用:DVB-S.2 系統 電壓 - 電源，模擬:- 電壓 - 電源，數字:- 安裝類型:- 封裝/外殼:模塊 供應商設備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| ADV7183KST | 制造商:Analog Devices 功能描述:Video Decoder 2ADC 10-Bit 80-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:VIDEO DECODER I.C. - Bulk |
| ADV7184 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat SDTV Video Decoder with Fast Switch Overlay Support |
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