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參數資料
| 型號： | ADV7324KSTZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顏色信號轉換 |
| 英文描述： | Multiformat 216 MHz Video Encoder with Six NSV 14-Bit DACs |
| 中文描述： | COLOR SIGNAL ENCODER, PQFP64 |
| 封裝： | LEAD FREE, MS-026BCD, LQFP-64 |
| 文件頁數： | 26/92頁 |
| 文件大小： | 992K |
| 代理商： | ADV7324KSTZ |
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ADV7324
Table 8. Registers 0x02 to 0x0F
SR7–
SR0
Register
0x02
Mode Register 0
Rev. 0 | Page 26 of 92
Bit Description
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
0
Bit 0
0
Register Setting
Zero must be written to
these bits.
Disabled.
Enabled.
Disable manual RGB matrix
adjust.
Enable manual RGB matrix
adjust.
No sync.
Sync on all RGB outputs.
RGB component outputs.
YPrPb component outputs.
No sync output.
Output SD syncs on
S_HSYNC, S_VSYNC,
S_BLANK pins.
No sync output.
Output HD, ED, syncs on
S_HSYNC, S_VSYNC.
LSB for GY.
LSB for RV.
LSB for BU.
LSB for GV.
LSB for GU.
Bit 9 to Bit 2 for GY.
Bit 9 to Bit 2 for GU.
Bit 9 to Bit 2 for GV.
Bit 9 to Bit 2 for BU.
Bit 9 to Bit 2 for RV.
0%
Reset Value
0x20
Test Pattern Black Bar
Manual RGB Matrix
Adjust
0
0
1
0x11, Bit 2 must
also be enabled.
1
Sync on RGB
1
RGB/YPrPb Output
SD Sync
0
1
0
1
0
1
HD Sync
0
1
0x03
0x04
RGB Matrix 0
RGB Matrix 1
x
x
x
x
x
x
0
x
x
x
x
x
x
0
x
x
x
x
x
x
0
x
x
x
x
x
x
0
x
x
x
x
x
x
0
x
x
x
x
x
x
0
x
x
x
x
x
x
x
0
x
x
x
x
x
x
x
0
0x03
0xF0
0x4E
0x0E
0x24
0x92
0x7C
0x00
0x05
0x06
0x07
0x08
0x09
0x0A
RGB Matrix 2
RGB Matrix 3
RGB Matrix 4
RGB Matrix 5
RGB Matrix 6
DAC A, B, C
Output Level
2
Positive Gain to DAC
Output Voltage
Negative Gain to
DAC Output Voltage
Positive Gain to DAC
Output Voltage
Negative Gain to
DAC Output Voltage
Reserved
Reserved
0
0
0
0
1
0
0
0
1
1
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
1
1
0
0
1
0
…
1
0
0
+0.018%
+0.036%
…
+7.382%
+7.5%
7.5%
0x0B
DAC D, E, F
Output Level
1
1
1
0
1
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
1
1
0
1
0
…
1
0
7.382%
7.364%
…
0.018%
0%
0x00
0
0
0
0
1
0
0
0
1
1
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
1
1
0
0
1
0
…
1
0
0
+0.018%
+0.036%
…
+7.382%
+7.5%
7.5%
0x0C
3
0x0D
3
0x0E
0x0F
1
1
1
0
1
1
0
1
0
1
0
0
1
1
0
0
0
1
1
0
0
0
1
0
0
0
0
1
0
0
0
1
1
1
0
1
0
…
1
1
0
7.382%
7.364%
…
0.018%
0x00
0x00
0x00
0x00
1
For more detail, refer to Appendix 7.
2
For more detail on the programmable output levels, refer to the Programmable DAC Gain Control section.
3
The register setting value must be written after power-up/reset.
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