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參數(shù)資料
型號(hào)： ADV7324KSTZ
廠商： ANALOG DEVICES INC
元件分類： 顏色信號(hào)轉(zhuǎn)換
英文描述： Multiformat 216 MHz Video Encoder with Six NSV 14-Bit DACs
中文描述： COLOR SIGNAL ENCODER, PQFP64
封裝： LEAD FREE, MS-026BCD, LQFP-64
文件頁(yè)數(shù)： 65/92頁(yè)
文件大小： 992K
代理商： ADV7324KSTZ
ADV7324
APPENDIX 1—COPY GENERATION MANAGEMENT SYSTEM
PS CGMS
Data Registers 2 to 0
[Subaddresses 0x21, 0x22, 0x23]
Rev. 0 | Page 65 of 92
525p
Using the vertical blanking interval 525p system, 525p CGMS
conforms to the CGMS-A EIA-J CPR1204-1 (March 1998)
transfer method of video identification information and to the
IEC61880 (1998) 525p/60 video system’s analog interface for the
video and accompanying data.
When PS CGMS is enabled [Subaddress 0x12, Bit 6 = 1], CGMS
data is inserted on Line 41. The 525p CGMS data registers are at
Address 0x21, Address 0x22, and Address 0x23.
625p
The 625p CGMS conforms to the IEC62375 (2004) 625p/50
video system’s analog interface for the video and accompanying
data using the vertical blanking interval.
When PS CGMS is enabled [Subaddress 0x12, Bit 6 = 1], CGMS
data is inserted on Line 43. The 625p CGMS data registers are at
Address 0x22 and Address 0x23.
HD CGMS
[Address 0x12, Bit 6]
The ADV7324 supports the copy generation management
system (CGMS) in HDTV mode (720p and 1080i) in
accordance with EIAJ CPR-1204-2.
The HD CGMS data registers are found at Address 0x021,
Address 0x22, and Address 0x23.
SD CGMS
Data Registers 2 to 0
[Subaddresses 0x59, 0x5A, 0x5B]
The ADV7324 supports the copy generation management
system (CGMS), conforming to the EIAJ CPR-1204 and
ARIB TR-B15 standards. CGMS data is transmitted on Line 20
of the odd fields and Line 283 of the even fields. Bit C/W05 and
Bit C/W06 control whether CGMS data is output on odd or
even fields. CGMS data can only be transmitted when the
ADV7324 is configured in NTSC mode. The CGMS data is
20 bits long. The CGMS data is preceded by a reference pulse of
the same amplitude and duration as a CGMS bit; see Figure 93.
720p System
CGMS data is applied to Line 24 of the luminance vertical
blanking interval.
1080i System
CGMS data is applied to Line 19 and Line 582 of the luminance
vertical blanking interval.
CGMS FUNCTIONALITY
If SD CGMS CRC [Address 0x59, Bit 4] or PS/HD CGMS CRC
[Subaddress 0x12, Bit 7] is set to Logic 1, the last six bits, C19 to
C14, which compose the 6-bit CRC check sequence, are
automatically calculated on the ADV7324. This calculation is
based on the lower 14 bits (C0 to C13) of the data in the data
registers and output with the remaining 14 bits to form the
complete 20 bits of the CGMS data. The calculation of the CRC
sequence is based on the polynomial x
6
+ x + 1 with a preset
value of 111111. If SD CGMS CRC [Address 0x59, Bit 4] and
PS/HD CGMS CRC [Address 0x12, Bit 7] are set to Logic 0, all
20 bits (C0 to C19) are output directly from the CGMS registers
(CRC must be manually calculated by the user).
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