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參數資料
| 型號： | ADV7324KSTZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顏色信號轉換 |
| 英文描述： | Multiformat 216 MHz Video Encoder with Six NSV 14-Bit DACs |
| 中文描述： | COLOR SIGNAL ENCODER, PQFP64 |
| 封裝： | LEAD FREE, MS-026BCD, LQFP-64 |
| 文件頁數： | 38/92頁 |
| 文件大?。?/td> | 992K |
| 代理商： | ADV7324KSTZ |
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ADV7324
INPUT CONFIGURATION
When 10-bit input data is applied, the following bits must be set
to 1:
Rev. 0 | Page 38 of 92
Address 0x13, Bit 2 (HD 10-bit enable)
Address 0x48, Bit 4 (SD 10-bit enable)
Note that the ADV7324 defaults to simultaneous SD and PS
upon power-up (Address[0x01]: Input Mode = 011).
SD ONLY
Address[0x01]: Input Mode = 000
In 8-/10-bit input mode, multiplexed data is input on Pin S9 to
Pin S0 (or Pin Y9 to Pin Y0, depending on Register Address 0x01,
Bit 7), with S0 being the LSB in 10-bit input mode (see Table 21).
Input standards supported are ITU-R BT.601/656. In 16-/20-bit
input mode, the Y pixel data is input on Pin S9 to Pin S2, and
CrCb data is input on Pin Y9 to Pin Y2 (see Table 21).
16-/20-Bit Mode Operation
When Register 0x01, Bit 7 = 0, CrCb data is input on the Y bus,
and Y data is input on the S bus. When Register 0x01, Bit 7 = 1,
CrCb data is input on the C bus, and Y data is input on Y bus.
The 27 MHz clock input must be input on Pin CLKIN_A. Input
sync signals are input on the S_VSYNC, S_HSYNC, and
S_BLANK pins.
Table 21. SD 8-/10-Bit and 16-/20-Bit Configurations
Parameter
8-/10-Bit Mode
Register 0x01, Bit 7 = 0
Y Bus
S Bus
656/601, YCrCb
C Bus
Register 0x01, Bit 7 = 1
Y Bus
656/601, YCrCb
S Bus
C Bus
Configuration
16-/20-Bit Mode
CrCb
Y
Y
CrCb
MPEG2
DECODER
CLKIN_A
S[9:0] OR Y[9:0]*
27MHz
3
10
YCrCb
ADV7324
*SELECTED BY ADDRESS 0x01, BIT 7
0
S_VSYNC,
S_HSYNC,
S_BLANK
Figure 48. SD Only Input Mode
PS ONLY OR HDTV ONLY
Address[0x01]: Input Mode = 001 or 010, Respectively
YCrCb PS, HDTV, or any other HD YCrCb data can be input in
4:2:2 or 4:4:4. In 4:2:2 input format, the Y data is input on Pin Y9
to Pin Y0, and the CrCb data is input on Pin C9 to Pin C0. In
4:4:4 input mode, Y data is input on Pin Y9 to Pin Y0, Cb data is
input on Pin C9 to Pin C0, and Cr data is input on Pin S9 to
Pin S0. If the YCrCb data does not conform to SMPTE 293M
(525p), ITU-R BT.1358M (625p), SMPTE 274M (1080i),
SMPTE 296M (720p), SMPTE 240M (1035i), or BTA-T1004/1362,
the async timing mode must be used. RGB data can only be
input in 4:4:4 format in PS or HDTV input modes when HD RGB
input is enabled. G data is input on Pin Y9 to Pin Y0, R data is
input on Pin S9 to Pin S0, and B data is input on Pin C9 to Pin C0.
The clock signal must be input on Pin CLKIN_A.
MPEG2
DECODER
CLKIN_A
C[9:0]
10
Cb
S[9:0]
Y[9:0]
INTERLACED TO
PS
YCrCb
10
Cr
10
Y
3
27MHz
ADV7324
0
P_VSYNC,
P_HSYNC,
P_BLANK
Figure 49. PS Input Mode
SIMULTANEOUS SD/PS OR SD/HDTV
Address[0x01]: Input Mode 011 (SD 10-Bit, PS 20-Bit), Input
Mode 101 (SD and HD, SD Oversampled), or Input Mode
110 (SD and HD, HD Oversampled)
YCrCb PS and HD data must be input in 4:2:2 format. In 4:2:2
input format, the HD Y data is input on Pin Y9 to Pin Y0, and
the HD CrCb data is input on Pin C9 to Pin C0. If PS 4:2:2 data is
inter-leaved onto a single 10-bit bus, Pin Y9 to Pin Y0 are used
for the input port. The input data is input at 27 MHz, with the
data being clocked upon the rising and falling edges of the input
clock. The input mode register at Address 0x01 is set accordingly.
If the YCrCb data does not conform to SMPTE 293M (525p),
ITU-R BT.1358M (625p), SMPTE 274M (1080i), SMPTE 296M
(720p), SMPTE 240M (1035i), or BTA-T1004, the async timing
mode must be used.
The 8- or 10-bit SD data must be compliant with ITU-R
BT.601/656 in 4:2:2 format. SD data is input on Pin S9 to Pin S0,
with S0 being the LSB. Using 8-bit input format, the data is
input on Pin S9 to Pin S2. The clock input for SD must be input
on CLKIN_A, and the clock input for HD must be input on
CLKIN_B. Synchronization signals are optional. SD syncs are
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