- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379696 > ATT3020-70M44I (Electronic Theatre Controls, Inc.) Field-Programmable Gate Arrays PDF資料下載
參數(shù)資料
| 型號(hào)： | ATT3020-70M44I |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | FPGA |
| 英文描述： | Field-Programmable Gate Arrays |
| 中文描述： | 現(xiàn)場(chǎng)可編程門陣列 |
| 文件頁數(shù)： | 10/80頁 |
| 文件大小： | 528K |
| 代理商： | ATT3020-70M44I |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁當(dāng)前第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
10
Lucent Technologies Inc.
Programmable Interconnect
(continued)
General-Purpose Interconnect
General-purpose interconnect, as shown in Figure 9,
consists of a grid of five horizontal and five vertical
metal segments located between the rows and col-
umns of logic and IOBs. Each segment is the height or
width of a logic block. Switching matrices join the ends
of these segments and allow programmed interconnec-
tions between the metal grid segments of adjoining
rows and columns. The switches of an unprogrammed
device are all nonconducting. The connections through
the switch matrix may be established by automatic or
interactive routing by selecting the desired pairs of
matrix pins to be connected or disconnected. The
legitimate switching matrix combinations for each pin
are indicated in Figure 10.
Special buffers within the general interconnect areas
provide periodic signal isolation and restoration for
improved performance of lengthy nets. The intercon-
nect buffers are available to propagate signals in either
direction on a given general interconnect segment.
These bidirectional (bidi) buffers are found adjacent to
the switching matrices, above and to the right. The
other PIPs adjacent to the matrices are accessed to or
from long lines. The development system automatically
defines the buffer direction based on the location of the
interconnection network source. The delay calculator in
the
ORCA
Foundry Development System automatically
calculates and displays the block, interconnect, and
buffer delays for any paths selected. Generation of the
simulation netlist with a worst-case delay model is also
provided by the development system.
Some of the interconnect PIPs are directional, as
indicated below:
I
ND is a nondirectional interconnection.
I
D:H->V is a PIP which drives from a horizontal to a
vertical line.
I
D:V->H is a PIP which drives from a vertical to a
horizontal line.
I
D:C->T is a T-PIP which drives from a cross of a
T to the tail.
I
D:CW is a corner PIP which drives in the clockwise
direction.
I
P0 indicates the PIP is nonconducting; P1 is on.
Figure 9. FPGA General-Purpose Interconnect
Figure 10. Switch Matrix Interconnection Options
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ATT3020-70M68I | Field-Programmable Gate Arrays |
| ATT3020-70M84I | Field-Programmable Gate Arrays |
| ATT3020-70S132I | Field-Programmable Gate Arrays |
| ATT3020-70S44I | Field-Programmable Gate Arrays |
| ATT3020-70S68I | Field-Programmable Gate Arrays |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ATT3020-70M68 | 制造商:ATandT 功能描述:FPGA, 64 CLBS, 2000 GATES, 84 MHz, PQCC68 |
| ATT3020-70M68I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays |
| ATT3020-70M84 | 制造商:AT&T 功能描述: 制造商:ATandT 功能描述: |
| ATT3020-70M84I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays |
| ATT3020-70N100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。