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參數(shù)資料
| 型號(hào)： | ATT3020-70M44I |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | FPGA |
| 英文描述： | Field-Programmable Gate Arrays |
| 中文描述： | 現(xiàn)場可編程門陣列 |
| 文件頁數(shù)： | 7/80頁 |
| 文件大小： | 528K |
| 代理商： | ATT3020-70M44I |
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Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Lucent Technologies Inc.
7
Configurable Logic Block
The array of configurable logic blocks (CLBs) provides
the functional elements from which the user’s logic is
constructed. The logic blocks are arranged in a matrix
within the perimeter of IOBs. The ATT3020 has 64 such
blocks arranged in eight rows and eight columns. The
ORCA
Foundry Development System is used to com-
pile the configuration data for loading into the internal
configuration memory to define the operation and inter-
connection of each block. User definition of CLBs and
their interconnecting networks may be done by auto-
matic translation from a schematic capture logic dia-
gram or optionally by installing library or user macros.
Each CLB has a combinatorial logic section, two flip-
flops, and an internal control section; see Figure 4
below. There are five logic inputs (.a, .b, .c, .d, and .e);
a common clock input (.k); an asynchronous direct
reset input (.rd); and an enable clock (.ec). All may be
driven from the interconnect resources adjacent to the
blocks. Each CLB also has two outputs (.x and .y)
which may drive interconnect networks.
Data input for either flip-flop within a CLB is supplied
from the function F or G outputs of the combinatorial
logic, or the block input, data-in (.di). Both flip-flops in
each CLB share the asynchronous reset (.rd) which,
when enabled and high, is dominant over clocked
inputs. All flip-flops are reset by the active-low chip
input,
RESET
, or during the configuration process.
The flip-flops share the enable clock (.ec) which, when
low, recirculates the flip-flops’ present states and inhib-
its response to the data-in or combinatorial function
inputs on a CLB. The user may enable these control
inputs and select their sources. The user may also
select the clock net input (.k), as well as its active
sense within each logic block. This programmable
inversion eliminates the need to route both phases of a
clock signal throughout the device. Flexible routing
allows use of common or individual CLB clocking.
The combinatorial logic portion of the logic block uses
a 32 x 1 look-up table to implement Boolean functions.
Variables selected from the five logic inputs and the
two internal block flip-flops are used as table address
inputs. The combinatorial propagation delay through
the network is independent of the logic function gener-
ated and is spike-free for single-input variable changes.
This technique can generate two independent logic
functions of up to four variables each as shown in Fig-
ure 5A, or a single function of five variables as shown in
Figure 5B, or some functions of seven variables as
shown in Figure 5C.
Figure 4. Configurable Logic Block
0
MUX
1
0
MUX
1
D
Q
RD
D
Q
RD
“1” (ENABLE)
DATA IN
LOGIC
VARIABLES
.a
.b
.c
.d
.e
ENABLE
CLOCK
CLOCK
QX
COMBINATORIAL
FUNCTION
QX
F
G
.x
.y
“0” (INHIBIT)
(GLOBAL RESET)
.ec
.k
.rd
.di
F
DIN
G
CLB OUTPUTS
QX
F
F
DIN
G
G
QY
5-3103(F)
DIRECT
RESET
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ATT3020-70M68I | Field-Programmable Gate Arrays |
| ATT3020-70M84I | Field-Programmable Gate Arrays |
| ATT3020-70S132I | Field-Programmable Gate Arrays |
| ATT3020-70S44I | Field-Programmable Gate Arrays |
| ATT3020-70S68I | Field-Programmable Gate Arrays |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ATT3020-70M68 | 制造商:ATandT 功能描述:FPGA, 64 CLBS, 2000 GATES, 84 MHz, PQCC68 |
| ATT3020-70M68I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays |
| ATT3020-70M84 | 制造商:AT&T 功能描述: 制造商:ATandT 功能描述: |
| ATT3020-70M84I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays |
| ATT3020-70N100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
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