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參數資料
| 型號： | ATT3020-70M44I |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | FPGA |
| 英文描述： | Field-Programmable Gate Arrays |
| 中文描述： | 現場可編程門陣列 |
| 文件頁數： | 65/80頁 |
| 文件大?。?/td> | 528K |
| 代理商： | ATT3020-70M44I |
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Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Lucent Technologies Inc.
65
Electrical Characteristics
(continued)
Note: The requirements in this timing diagram are extremely relaxed; data need not be held beyond the rising edge of
WS
.
BUSY
will go active
within 60 ns after the end of
WS
.
BUSY
will stay active for several microseconds.
WS
may be asserted immediately after the end of
BUSY
.
Figure 38. Peripheral Mode Switching Characteristics
Notes:
At powerup, V
CC
must rise from 2.0 V to V
CC
minimum in less than 25 ms. If this is not possible, configuration can be delayed by holding
RESET
low until V
CC
has reached 4.0 V. A very long V
CC
rise time of >100 ms, or a nonmonotonically rising V
CC
may require a >1 μs high level on
RESET
, followed by >6 μs low level on
RESET
and D/
P
after V
CC
has reached 4.0 V.
Configuration must be delayed until the
INIT
of all FPGAs is high.
Time from end of
WS
to CCLK cycle for the new byte of data depends on completion of previous byte processing and the phase of the
internal timing generator for CCLK.
CCLK and DOUT timing is tested in slave mode.
T
BUSY
indicates that the double-buffered parallel-to-serial converter is not yet ready to receive new data. The shortest T
BUSY
occurs when a
byte is loaded into an empty parallel-to-serial converter. The longest T
BUSY
occurs when a new word is loaded into the input register before the
second-level buffer has started shifting out data.
Table 28. Peripheral Mode Switching Characteristics
Signal
Write Signal
Description
Symbol
Min
Max
Unit
Effective Write Time Required
(Assertion of
CS0
,
CS1
, CS2,
WS
)
DIN Setup Time Required
DIN Hold TIme Required
RDY/
BUSY
Delay after End of
WS
Earliest Next
WS
after End of
BUSY
BUSY
Low Time Generated
1
2
3
4
5
6
T
CA
T
DC
T
CD
T
WTRB
T
RBWT
T
BUSY
100
60
0
—
0
2.5
—
—
—
60
—
9
ns
ns
ns
ns
ns
D[7:0]
RDY/
BUSY
CCLK
Periods
5-3129(F)
CS1/CS0
CS2
WS
D[7:0]
CCLK
RDY/BUSY
DOUT
T
CA
T
DC
T
CD
VALID
T
RBWT
T
WTRB
T
BUSY
GROUP OF
8 CCLKs
1
4
3
6
5
2
相關PDF資料 |
PDF描述 |
|---|---|
| ATT3020-70M68I | Field-Programmable Gate Arrays |
| ATT3020-70M84I | Field-Programmable Gate Arrays |
| ATT3020-70S132I | Field-Programmable Gate Arrays |
| ATT3020-70S44I | Field-Programmable Gate Arrays |
| ATT3020-70S68I | Field-Programmable Gate Arrays |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ATT3020-70M68 | 制造商:ATandT 功能描述:FPGA, 64 CLBS, 2000 GATES, 84 MHz, PQCC68 |
| ATT3020-70M68I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays |
| ATT3020-70M84 | 制造商:AT&T 功能描述: 制造商:ATandT 功能描述: |
| ATT3020-70M84I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays |
| ATT3020-70N100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
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