- 您現在的位置：買賣IC網 > PDF目錄379831 > CDC9171 (Texas Instruments, Inc.) DVD System Clock Synthesizerers(DVD系統時鐘合成器) PDF資料下載
參數資料
| 型號： | CDC9171 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | DVD System Clock Synthesizerers(DVD系統時鐘合成器) |
| 中文描述： | DVD系統時鐘Synthesizerers（影碟系統時鐘合成器） |
| 文件頁數： | 1/5頁 |
| 文件大小： | 95K |
| 代理商： | CDC9171 |
CDC9171
DVD SYSTEM CLOCK SYNTHESIZER
SCAS558B – DECEMBER 1995 – REVISED OCTOBER 1996
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Two Integrated PLLs Provide All Digital
Video Disk (DVD) System Frequencies
Two 27-MHz Reference Clock Outputs
One 18.432-MHz Reference Clock Output
One 33.875-MHz Reference Clock Output
Output Clock Frequencies Derived From an
18.432-MHz Crystal Input
3.3-V CMOS Outputs
Separate Analog Core and Output Supply
Voltage
Internal Loop Filters for Phase-Lock Loops
Eliminate the Need for External
Components
description
The CDC9171 is a high-performance clock synthesizer that generates the required clock signals needed for
a DVD system.
The CDC9171 generates all output frequencies from an 18.432-MHz crystal. The 18.432-MHz (FCLK1)
reference clock output is buffered from the integrated oscillators. Two integrated phase-lock loops (PLL)
synthesize the 27-MHz (FCLK2, FCLK3) and the 33.868-MHz (FCLK4) reference clock outputs from the
18.4320-MHz crystal. The oscillator and PLLs can be bypassed in the TEST mode. When TEST is high, input
1X1 is buffered to all outputs.
All clock outputs provide low-jitter clock signals for reliable clock operation. PWRDN is used to disable the PLLs
and output buffers. When low, PWRDN disables the integrated PLLs and forces all outputs to a logic-low state.
Because the CDC9171 is based on PLL circuitry, it requires a stabilization time to achieve phase lock of the PLL.
This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal
at the 1X1 input and upon activation, following the transition of PWRDN to a logic-high state.
FUNCTION TABLE
INPUTS
OUTPUTS
PWRDN
L
H
H
H
TEST
X
L
H
H
1X1
X
FCLK1
L
18.432 MHz
L
H
FCLK(2–3)
L
27 MHz
L
H
FLCK4
L
33.868 MHz
L
H
18.432 MHz
L
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
GND
1X1
1X2
V
CC
GND
PWRDN
GND
V
CC
V
CC
GND
GND
GND
FCLK1
TEST
FCLK2
V
CC
GND
NC
GND
FCLK3
V
CC
AGND
AV
CC
FCLK4
DB PACKAGE
(TOP VIEW)
NC – No internal connection
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
1996, Texas Instruments Incorporated
相關PDF資料 |
PDF描述 |
|---|---|
| CDC9441 | DVD System Clock Synthesizerers(PC時鐘合成器/驅動器(SDRAM 時鐘支持)) |
| CDC9449 | PC Motherboard Clock Sythesizer/Drivers with SDRAM Clock Support(PC時鐘合成器/驅動器(SDRAM 時鐘支持)) |
| CDC9841 | PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER WITH 3-STATE OUTPUTS |
| CDC9841DW | PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER WITH 3-STATE OUTPUTS |
| CDC9841DWR | PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER WITH 3-STATE OUTPUTS |
相關代理商/技術參數 |
參數描述 |
|---|---|
| CDC921 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DIRECT RAMBUSE CLOCK GENERATOR |
| CDC921DL | 制造商:Texas Instruments 功能描述: |
| CDC922 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DIRECT RAMBUSE CLOCK GENERATOR |
| CDC922DL | 制造商:TI 制造商全稱:Texas Instruments 功能描述:133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS |
| CDC922DLR | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
發布緊急采購，3分鐘左右您將得到回復。