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參數(shù)資料
| 型號(hào)： | CGS410 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Programmable Clock Generator |
| 中文描述： | 可編程時(shí)鐘發(fā)生器 |
| 文件頁(yè)數(shù)： | 1/18頁(yè) |
| 文件大小： | 285K |
| 代理商： | CGS410 |
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TL/F/11919
C
September 1995
CGS410
Programmable Clock Generator
General Description
The CGS410 is a programmable clock generator which pro-
duces a variable frequency clock output for use in graphics,
disk drives and clock synchronizing applications. The
CGS410 produces output clocks in CMOS and differential
formats. The user is able to program the differential output
levels to best suit the levels of the interfacing device. A
common configuration allows PCLK to emulate positive ECL
logic levels, eliminating the need for TTL to ECL translation.
The CGS410 is referenced off the XTLIN input which can be
configured for either external crystal or external oscillator
support. All internal frequency generation is referenced from
the XTLIN input. The CGS410 can also be driven by
EXTCLK as desired. EXTCLK may serve as the source from
a fixed clock (for passthru mode), or as an external VCO
input.
The CGS410 contains three internal user-selectable low
pass filters (LPFs). A fourth option allows for the use of an
external LPF configuration. Use of the internal filters greatly
simplifies layout, reduces board real estate, and minimizes
part count. A programmable polarity charge pump allows
the user to optimize the optional external LPF circuitry.
The primary loop structure of the CGS410 consists of pro-
grammable N and R dividers. Both are contiguous; N can be
any value between 2 and 16383, and R can be any value
between 1 and 1023. Additional dividers of the internal
VCO
allow
individual
programmability
CMOSDPCLK, and LCLK outputs.
for
the
PCLK,
An additional advantage of the CGS410 is its ability to per-
form smooth, glitch-free clock output changes as the user
selects passthru clock sources or changes the VCO
frequency. A real-time synchronous load clock enable
(LCLKDEN) control input allows for the enabling and dis-
abling of the LCLK output. This is suitable for applications
which require the removal of an active LCLK during the
blanking portion of a screen refresh.
On power-up the XTLIN frequency is internally divided by
two and routed to the PCLK outputs, providing a known
power-up output frequency with a 50% duty cycle. The
CGS410 is programmed by a serial stream of data. A serial
bit read can verify the contents of the register.
Features
Y
Fully programmable frequency generator
Y
Provides frequencies to 135 MHz
Y
Configurable high-speed complementary clock outputs
Y
CMOS output clocks
Y
Glitch-free transitions for clock changes
Y
Powers up in a known state
Y
Single supply (
a
5V) operation
Y
Low current draw, ideal for battery applications
Y
Read/write control register
Y
Internal VCO and loop filters
Connection Diagram
TL/F/11919–1
Important Note:
This device is sensitive to noise on certain pins, especially FREQCTL, FILTER, AVDD, and AGND. Special care must be taken with board
layout for optimum performance.
TRI-STATE
é
is a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation
RRD-B30M115/Printed in U. S. A.
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| CGS412T250V4L | 功能描述:鋁質(zhì)電解電容器-螺旋式接線端 250V 4100uF RoHS:否 制造商:Cornell Dubilier 電容:2400 uF 容差:- 10 %, + 50 % 電壓額定值:450 V ESR:38 mOhms 工作溫度范圍:- 40 C to + 85 C 系列:CGS 直徑:76 mm (3 in) 長(zhǎng)度:143 mm (5.625 in) 引線間隔:31.75 mm (1.25 in) 產(chǎn)品:Computer Grade Electrolytic Capacitors |
| CGS412T250V5L | 功能描述:鋁質(zhì)電解電容器-螺旋式接線端 4100uF 250V-10+50% RoHS:否 制造商:Cornell Dubilier 電容:2400 uF 容差:- 10 %, + 50 % 電壓額定值:450 V ESR:38 mOhms 工作溫度范圍:- 40 C to + 85 C 系列:CGS 直徑:76 mm (3 in) 長(zhǎng)度:143 mm (5.625 in) 引線間隔:31.75 mm (1.25 in) 產(chǎn)品:Computer Grade Electrolytic Capacitors |
| CGS412T300W4C | 功能描述:鋁質(zhì)電解電容器-螺旋式接線端 4100uF 300V-10+50% RoHS:否 制造商:Cornell Dubilier 電容:2400 uF 容差:- 10 %, + 50 % 電壓額定值:450 V ESR:38 mOhms 工作溫度范圍:- 40 C to + 85 C 系列:CGS 直徑:76 mm (3 in) 長(zhǎng)度:143 mm (5.625 in) 引線間隔:31.75 mm (1.25 in) 產(chǎn)品:Computer Grade Electrolytic Capacitors |
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