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參數資料
| 型號： | CY7C1302DV25 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 9-Mbit Burst of Two Pipelined SRAMs with QDR(帶QDRTM結構的9-Mbit，同步Pipelined SRAMs) |
| 中文描述： | 9兆位的兩項國防評估報告（帶QDRTM結構的9兆位，同步流水線突發靜態存儲器靜態存儲器流水線） |
| 文件頁數： | 1/18頁 |
| 文件大小： | 386K |
| 代理商： | CY7C1302DV25 |
9-Mbit Burst of Two Pipelined SRAMs
with QDR Architecture
CY7C1302DV25
Cypress Semiconductor Corporation
Document #: 38-05625 Rev. *A
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised March 23, 2006
Features
Separate independent Read and Write data ports
— Supports concurrent transactions
167-MHz clock for high bandwidth
— 2.5 ns Clock-to-Valid access time
2-word burst on all accesses
Double Data Rate (DDR) interfaces on both Read and
Write ports (data transferred at 333 MHz) @ 167 MHz
Two input clocks (K and K) for precise DDR timing
— SRAM uses rising edges only
Two input clocks for output data (C and C) to minimize
clock-skew and flight-time mismatches.
Single multiplexed address input bus latches address
inputs for both Read and Write ports
Separate Port Selects for depth expansion
Synchronous internally self-timed writes
2.5V core power supply with HSTL Inputs and Outputs
Available in 165-ball FBGA package (13 x 15 x 1.4 mm)
Variable drive HSTL output buffers
Expanded HSTL output voltage (1.4V–1.9V)
JTAG Interface
Configurations
CY7C1302DV25 – 512K x 18
Functional Description
The CY7C1302DV25 is a 2.5V Synchronous Pipelined SRAM
equipped with QDR architecture. QDR architecture consists
of two separate ports to access the memory array. The Read
port has dedicated data outputs to support Read operations
and the Write Port has dedicated data inputs to support Write
operations. Access to each port is accomplished through a
common address bus. The Read address is latched on the
rising edge of the K clock and the Write address is latched on
the rising edge of K clock. QDR has separate data inputs and
data outputs to completely eliminate the need to “turn-around”
the data bus required with common I/O devices. Accesses to
the CY7C1302DV25 Read and Write ports are completely
independent of one another. All accesses are initiated
synchronously on the rising edge of the positive input clock
(K). In order to maximize data throughput, both Read and
Write ports are equipped with DDR interfaces. Therefore, data
can be transferred into the device on every rising edge of both
input clocks (K and K) and out of the device on every rising
edge of the output clock (C and C, or K and K in a single clock
domain) thereby maximizing performance while simplifying
system design. Each address location is associated with two
18-bit words that burst sequentially into or out of the device.
Depth expansion is accomplished with a Port Select input for
each port. Each Port Select allows each port to operate
independently.
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
256Kx18
Memory
Array
CLK
Gen.
A
(17:0)
K
K
Control
Logic
Address
Register
D
[17:0]
R
Read Data Reg.
RPS
WPS
BWS
0
BWS
1
Q
[17:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
18
18
18
36
Write
Data Reg
18
Vref
W
Write
Data Reg
256Kx18
Memory
Array
18
18
A
(17:0)
18
18
C
C
Logic Block Diagram (
CY7C1302DV25
)
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PDF描述 |
|---|---|
| CY7C1302V25 | 9-Mb Pipelined SRAM with QDR Architecture(帶QDR結構的9-M位流水線式 SRAM) |
| CY7C1305BV25 | 18-Mbit Burst of 4 Pipelined SRAM with QDR Architecture(18Mbit，Burst of 4，QDR結構，流水線SRAM) |
| CY7C131-15NC | CAP 10UF 63V ELECT EB RADIAL |
| CY7C141-15NC | 1K x 8 Dual-Port Static Ram |
| CY7C1312AV18 | 18-Mb QDR-II SRAM 2-Word Burst Architecture(18-Mb QDR-II SRAM（2-Word Burst結構）) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| CY7C1302DV25-167BZC | 功能描述:靜態隨機存取存儲器 512Kx18 2.5V QDR 靜態隨機存取存儲器 COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1302DV25-167BZXC | 功能描述:靜態隨機存取存儲器 9MB (512Kbx18) 2.5V, 167MHz RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1302DV25-250BZC | 功能描述:靜態隨機存取存儲器 512Kx18 2.5V QDR 靜態隨機存取存儲器 COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1302V25-167BZC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Dual 2.5V 9M-Bit 512K x 18 2.5ns 165-Pin FBGA |
| CY7C1303BV25-167BZC | 功能描述:靜態隨機存取存儲器 1Mx18 2.5V QDR 靜態隨機存取存儲器 COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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