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參數(shù)資料
| 型號(hào)： | EFM32-TG840F32-SK |
| 廠商： | Energy Micro |
| 文件頁數(shù)： | 31/136頁 |
| 文件大小： | 0K |
| 描述： | IC MICRO KIT GECKO 64QFN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Tiny Gecko |
| 套件類型： | 微控制器 |
| 值： | 2 件 - 閃存 - 32KB |
| 包裝： | 紙板盒 |
| 安裝類型： | 表面貼裝 |
| 包括封裝： | 64-QFN |
| 工具箱內(nèi)容： | (2) 914-1036-2-ND - MCU 32BIT 32KB FLASH 64-QFN |
| 其它名稱： | 914-1020 |
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...the world's most energy friendly microcontrollers
2011-02-04 - d0002_Rev1.00
126
www.energymicro.com
Implementation-specific
The behavior is not architecturally defined, and does not have to be
documented by individual implementations. Used when there are a number
of implementation options available and the option chosen does not affect
software compatibility.
Index register
In some load and store instruction descriptions, the value of this register
is used as an offset to be added to or subtracted from the base register
value to form the address that is sent to memory. Some addressing modes
optionally enable the index register value to be shifted prior to the addition
or subtraction.
See Also Base register.
Instruction cycle count
The number of cycles that an instruction occupies the Execute stage of the
pipeline.
Interrupt handler
A program that control of the processor is passed to when an interrupt occurs.
Interrupt vector
One of a number of fixed addresses in low memory, or in high memory if high
vectors are configured, that contains the first instruction of the corresponding
interrupt handler.
Little-endian (LE)
Byte ordering scheme in which bytes of increasing significance in a data word
are stored at increasing addresses in memory.
See Also Big-endian, Byte-invariant, Endianness.
Little-endian memory
Memory in which:
a byte or halfword at a word-aligned address is the least significant byte
or halfword within the word at that address
a byte at a halfword-aligned address is the least significant byte within the
halfword at that address.
See Also Big-endian memory.
Load/store architecture
A processor architecture where data-processing operations only operate on
register contents, not directly on memory contents.
Memory Protection Unit
(MPU)
Hardware that controls access permissions to blocks of memory. An MPU
does not perform any address translation.
Prefetching
In pipelined processors, the process of fetching instructions from memory to
fill up the pipeline before the preceding instructions have finished executing.
Prefetching an instruction does not mean that the instruction has to be
executed.
Read
Reads are defined as memory operations that have the semantics of a
load. Reads include the Thumb instructions LDM, LDR, LDRSH, LDRH, LDRSB,
LDRB
, and POP.
Region
A partition of memory space.
Reserved
A field in a control register or instruction format is reserved if the field is to
be defined by the implementation, or produces Unpredictable results if the
contents of the field are not zero. These fields are reserved for use in future
extensions of the architecture or are implementation#specific. All reserved
bits not used by the implementation must be written as 0 and read as 0.
Should Be One (SBO)
Write as 1, or all 1s for bit fields, by software. Writing as 0 produces
Unpredictable results.
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| EFM32-TG230F32-SK | IC MICRO KIT GECKO 64QFN |
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| 1267 X 6" | TAPE ALUMINUM FOIL 6" X 1FT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EFM32TG840F32-T | 制造商:Energy Micro AS 功能描述:IC MCU 32BIT 32KB FLASH 64QFN |
| EFM32TG840F8 | 功能描述:ARM微控制器 - MCU 8KB Flash 2KB RAM RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:72 MHz 程序存儲(chǔ)器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風(fēng)格:SMD/SMT |
| EFM32TG840F8-QFN64 | 制造商:Energy Micro AS 功能描述:8 FLASH, USART + UART 2, QFN64 - Tape and Reel 制造商:Energy Micro AS 功能描述:IC MCU 32BIT 8KB FLASH 64QFN |
| EFM32TG840F8-QFN64T | 制造商:Energy Micro AS 功能描述:32 BIT ARM MPU, TINY GECKO - Trays |
| EFM32TG840F8-QFN64-T | 制造商:Energy Micro AS 功能描述:IC MCU 32BIT 8KB FLASH 64QFN |
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