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參數(shù)資料
| 型號(hào)： | EPF10K20TI144-4N |
| 廠商： | Altera |
| 文件頁數(shù)： | 42/128頁 |
| 文件大小： | 0K |
| 描述： | IC FLEX 10K FPGA 20K 144-TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | FLEX-10K® |
| LAB/CLB數(shù)： | 144 |
| 邏輯元件/單元數(shù)： | 1152 |
| RAM 位總計(jì)： | 12288 |
| 輸入/輸出數(shù)： | 102 |
| 門數(shù)： | 63000 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 144-LQFP |
| 供應(yīng)商設(shè)備封裝： | 144-TQFP（20x20） |
| 其它名稱： | 544-2221 |
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Altera Corporation
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Normal Mode
The normal mode is suitable for general logic applications and wide
decoding functions that can take advantage of a cascade chain. In normal
mode, four data inputs from the LAB local interconnect and the carry-in
are inputs to a four-input LUT. The Compiler automatically selects the
carry-in or the DATA3 signal as one of the inputs to the LUT. The LUT
output can be combined with the cascade-in signal to form a cascade chain
through the cascade-out signal. Either the register or the LUT can be used
to drive both the local interconnect and the FastTrack Interconnect at the
same time.
The LUT and the register in the LE can be used independently; this feature
is known as register packing. To support register packing, the LE has two
outputs; one drives the local interconnect and the other drives the
FastTrack Interconnect. The DATA4 signal can drive the register directly,
allowing the LUT to compute a function that is independent of the
registered signal; a three-input function can be computed in the LUT, and
a fourth independent signal can be registered. Alternatively, a four-input
function can be generated, and one of the inputs to this function can be
used to drive the register. The register in a packed LE can still use the clock
enable, clear, and preset signals in the LE. In a packed LE, the register can
drive the FastTrack Interconnect while the LUT drives the local
interconnect, or vice versa.
Arithmetic Mode
The arithmetic mode offers 2 three-input LUTs that are ideal for
implementing adders, accumulators, and comparators. One LUT
computes a three-input function, and the other generates a carry output.
two data inputs from the LAB local interconnect to generate a
combinatorial or registered output. For example, in an adder, this output
is the sum of three signals: a, b, and carry-in. The second LUT uses the
same three signals to generate a carry-out signal, thereby creating a carry
chain. The arithmetic mode also supports simultaneous use of the cascade
chain.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| RSC44DRYH-S13 | CONN EDGECARD 88POS .100 EXTEND |
| RMC44DRYH-S13 | CONN EDGECARD 88POS .100 EXTEND |
| EPF10K20TI144-4 | IC FLEX 10K FPGA 20K 144-TQFP |
| RSC60DREN | CONN EDGECARD 120POS .100 EYELET |
| A54SX32A-TQG144 | IC FPGA 249I/O 144TQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EPF10K250A | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Embedded Programmable Logic Device Family |
| EPF10K250ABC600-2 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| EPF10K250AGC599-1 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Altera Corporation 功能描述: |
| EPF10K250AGC599-2 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| EPF10K250AGC599-3 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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