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參數資料
型號: EPF10K20TI144-4N
廠商: Altera
文件頁數: 54/128頁
文件大?。?/td> 0K
描述: IC FLEX 10K FPGA 20K 144-TQFP
產品培訓模塊: Three Reasons to Use FPGA's in Industrial Designs
標準包裝: 60
系列: FLEX-10K®
LAB/CLB數: 144
邏輯元件/單元數: 1152
RAM 位總計: 12288
輸入/輸出數: 102
門數: 63000
電源電壓: 4.5 V ~ 5.5 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 144-LQFP
供應商設備封裝: 144-TQFP(20x20)
其它名稱: 544-2221
Altera Corporation
31
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Each IOE selects the clock, clear, clock enable, and output enable controls
from a network of I/O control signals called the peripheral control bus.
The peripheral control bus uses high-speed drivers to minimize signal
skew across devices; it provides up to 12 peripheral control signals that
can be allocated as follows:
Up to eight output enable signals
Up to six clock enable signals
Up to two clock signals
Up to two clear signals
If more than six clock enable or eight output enable signals are required,
each IOE on the device can be controlled by clock enable and output
enable signals driven by specific LEs. In addition to the two clock signals
available on the peripheral control bus, each IOE can use one of two
dedicated clock pins. Each peripheral control signal can be driven by any
of the dedicated input pins or the first LE of each LAB in a particular row.
In addition, an LE in a different row can drive a column interconnect,
which causes a row interconnect to drive the peripheral control signal.
The chip-wide reset signal will reset all IOE registers, overriding any other
control signals.
Tables 8 and 9 list the sources for each peripheral control signal, and the
rows that can drive global signals. These tables also show how the output
enable, clock enable, clock, and clear signals share 12 peripheral control
signals.
相關PDF資料
PDF描述
RSC44DRYH-S13 CONN EDGECARD 88POS .100 EXTEND
RMC44DRYH-S13 CONN EDGECARD 88POS .100 EXTEND
EPF10K20TI144-4 IC FLEX 10K FPGA 20K 144-TQFP
RSC60DREN CONN EDGECARD 120POS .100 EYELET
A54SX32A-TQG144 IC FPGA 249I/O 144TQFP
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