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參數(shù)資料
| 型號(hào)： | EPF10K20TI144-4N |
| 廠商： | Altera |
| 文件頁(yè)數(shù)： | 43/128頁(yè) |
| 文件大小： | 0K |
| 描述： | IC FLEX 10K FPGA 20K 144-TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | FLEX-10K® |
| LAB/CLB數(shù)： | 144 |
| 邏輯元件/單元數(shù)： | 1152 |
| RAM 位總計(jì)： | 12288 |
| 輸入/輸出數(shù)： | 102 |
| 門數(shù)： | 63000 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 144-LQFP |
| 供應(yīng)商設(shè)備封裝： | 144-TQFP（20x20） |
| 其它名稱： | 544-2221 |
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Altera Corporation
21
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Up/Down Counter Mode
The up/down counter mode offers counter enable, clock enable,
synchronous up/down control, and data loading options. These control
signals are generated by the data inputs from the LAB local interconnect,
the carry-in signal, and output feedback from the programmable register.
The Up/down counter mode uses 2 three-input LUTs: one generates the
counter data, and the other generates the fast carry bit. A 2-to-1
multiplexer provides synchronous loading. Data can also be loaded
asynchronously with the clear and preset register control signals, without
using the LUT resources.
Clearable Counter Mode
The clearable counter mode is similar to the up/down counter mode, but
supports a synchronous clear instead of the up/down control. The clear
function is substituted for the cascade-in signal in the up/down counter
mode. Clearable counter mode uses 2 three-input LUTs: one generates the
counter data, and the other generates the fast carry bit. Synchronous
loading is provided by a 2-to-1 multiplexer. The output of this multiplexer
is ANDed with a synchronous clear signal.
Internal Tri-State Emulation
Internal tri-state emulation provides internal tri-stating without the
limitations of a physical tri-state bus. In a physical tri-state bus, the
tri-state buffers’ output enable (OE) signals select which signal drives the
bus. However, if multiple OE signals are active, contending signals can be
driven onto the bus. Conversely, if no OE signals are active, the bus will
float. Internal tri-state emulation resolves contending tri-state buffers to a
low value and floating buses to a high value, thereby eliminating these
problems. The Altera software automatically implements tri-state bus
functionality with a multiplexer.
Clear & Preset Logic Control
Logic for the programmable register’s clear and preset functions is
controlled by the DATA3, LABCTRL1, and LABCTRL2 inputs to the LE. The
clear and preset control structure of the LE asynchronously loads signals
into a register. Either LABCTRL1 or LABCTRL2 can control the
asynchronous clear. Alternatively, the register can be set up so that
LABCTRL1
implements an asynchronous load. The data to be loaded is
driven to DATA3; when LABCTRL1 is asserted, DATA3 is loaded into the
register.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| RSC44DRYH-S13 | CONN EDGECARD 88POS .100 EXTEND |
| RMC44DRYH-S13 | CONN EDGECARD 88POS .100 EXTEND |
| EPF10K20TI144-4 | IC FLEX 10K FPGA 20K 144-TQFP |
| RSC60DREN | CONN EDGECARD 120POS .100 EYELET |
| A54SX32A-TQG144 | IC FPGA 249I/O 144TQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EPF10K250A | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Embedded Programmable Logic Device Family |
| EPF10K250ABC600-2 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| EPF10K250AGC599-1 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Altera Corporation 功能描述: |
| EPF10K250AGC599-2 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| EPF10K250AGC599-3 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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