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參數(shù)資料
| 型號： | EPF10K20TI144-4N |
| 廠商： | Altera |
| 文件頁數(shù)： | 60/128頁 |
| 文件大小： | 0K |
| 描述： | IC FLEX 10K FPGA 20K 144-TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | FLEX-10K® |
| LAB/CLB數(shù)： | 144 |
| 邏輯元件/單元數(shù)： | 1152 |
| RAM 位總計(jì)： | 12288 |
| 輸入/輸出數(shù)： | 102 |
| 門數(shù)： | 63000 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 144-LQFP |
| 供應(yīng)商設(shè)備封裝： | 144-TQFP（20x20） |
| 其它名稱： | 544-2221 |
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Altera Corporation
37
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
ClockLock &
ClockBoost
Features
To support high-speed designs, selected FLEX 10K devices offer optional
ClockLock and ClockBoost circuitry containing a phase-locked loop (PLL)
that is used to increase design speed and reduce resource usage. The
ClockLock circuitry uses a synchronizing PLL that reduces the clock delay
and skew within a device. This reduction minimizes clock-to-output and
setup times while maintaining zero hold times. The ClockBoost circuitry,
which provides a clock multiplier, allows the designer to enhance device
area efficiency by sharing resources within the device. The ClockBoost
feature allows the designer to distribute a low-speed clock and multiply
that clock on-device. Combined, the ClockLock and ClockBoost features
provide significant improvements in system performance and
bandwidth.
The ClockLock and ClockBoost features in FLEX 10K devices are enabled
through the Altera software. External devices are not required to use these
features. The output of the ClockLock and ClockBoost circuits is not
available at any of the device pins.
The ClockLock and ClockBoost circuitry locks onto the rising edge of the
incoming clock. The circuit output can only drive the clock inputs of
registers; the generated clock cannot be gated or inverted.
The dedicated clock pin (GCLK1) supplies the clock to the ClockLock and
ClockBoost circuitry. When the dedicated clock pin is driving the
ClockLock or ClockBoost circuitry, it cannot drive elsewhere in the device.
In designs that require both a multiplied and non-multiplied clock, the
clock trace on the board can be connected to GCLK1. With the Altera
software, GCLK1 can feed both the ClockLock and ClockBoost circuitry in
the FLEX 10K device. However, when both circuits are used, the other
clock pin (GCLK0) cannot be used. Figure 17 shows a block diagram of
how to enable both the ClockLock and ClockBoost circuits in the Altera
software. The example shown is a schematic, but a similar approach
applies for designs created in AHDL, VHDL, and Verilog HDL. When the
ClockLock and ClockBoost circuits are used simultaneously, the input
frequency parameter must be the same for both circuits. In Figure 17, the
input frequency must meet the requirements specified when the
ClockBoost multiplication factor is two.
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