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參數(shù)資料
型號(hào): GS1559
廠商: Gennum Corporation
英文描述: GS1559 HD-LINX-TM II Multi-Rate Deserializer with Loop-Through Cable Driver
中文描述: GS1559的HD - LINX進(jìn)程,商標(biāo)第二多速率解串器與環(huán)通電纜驅(qū)動(dòng)器
文件頁數(shù): 46/74頁
文件大小: 686K
代理商: GS1559
GS1559 Data Sheet
30572 - 4
July 2005
46 of 74
4.10.3 SMPTE 352M Payload Identifier
The GS1559 can receive and detect the presence of the SMPTE 352M payload
identifier ancillary data packet. This four word payload identifier packet may be
used to indicate the transport mechanism, frame rate and line scanning / sampling
structure.
Upon reception of this packet, the device will extract the four words describing the
video format being transported and make this information available to the host
interface via the four VIDEO_FORMAT_OUT registers (
Table 4-6
).
The VIDEO_FORMAT_OUT registers will only be updated if the received
checksum is the same as the locally calculated checksum.
These registers will be cleared to zero, indicating an undefined format, if the device
loses lock to the input data stream (LOCKED = LOW), or if the SMPTE_BYPASS
pin is asserted LOW. This is also the default setting after device reset.
The SMPTE 352M packet should be received once per field for interlaced systems
and once per frame for progressive systems. If the packet is not received for two
complete video frames, the VIDEO_FORMAT_OUT registers will be cleared to
zero.
ANC_TYPE4
Address: 008h
15-8
ANC_TYPE4[15:8]
Used to program the DID for ancillary data detection at
the YANC and CANC output
R/W
0
7-0
ANC_TYPE4[7:0]
Used to program the SDID for ancillary data detection
at the YANC and CANC output.
Should be set to zero if no SDID is present in the
ancillary data packet to be detected.
R/W
0
ANC_TYPE5
Address: 009h
15-8
ANC_TYPE5[15:8]
Used to program the DID for ancillary data detection at
the YANC and CANC output
R/W
0
7-0
ANC_TYPE5[7:0]
Used to program the SDID for ancillary data detection
at the YANC and CANC output.
Should be set to zero if no SDID is present in the
ancillary data packet to be detected.
R/W
0
Table 4-5: Host Interface Description for Programmable Ancillary Data Type Registers (Continued)
Register Name
Bit
Name
Description
R/W
Default
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