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參數資料
| 型號： | GS1559 |
| 廠商： | Gennum Corporation |
| 英文描述： | GS1559 HD-LINX-TM II Multi-Rate Deserializer with Loop-Through Cable Driver |
| 中文描述： | GS1559的HD - LINX進程，商標第二多速率解串器與環通電纜驅動器 |
| 文件頁數： | 61/74頁 |
| 文件大小： | 686K |
| 代理商： | GS1559 |
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GS1559 Data Sheet
30572 - 4
July 2005
61 of 74
4.11 Parallel Data Outputs
Data outputs leave the device on the rising edge of PCLK as shown in
Figure 4-7
and
Figure 4-8
.
The data may be scrambled or unscrambled, framed or unframed, and may be
presented in 10-bit or 20-bit format. The output data bus width is controlled
independently from the internal data bus width by the 20bit/10bit input pin.
Likewise, the output data format is defined by the setting of the external SD/HD,
SMPTE_BYPASS and DVB_ASI pins. Recall that in slave mode, these pins are set
by the application layer as inputs to the device. In master mode, however, the
GS1559 sets these pins as output status signals.
4.11.1 Parallel Data Bus Buffers
The parallel data outputs of the GS1559 are driven by high-impedance buffers
which support both LVTTL and LVCMOS levels. These buffers use a separate
power supply of +3.3V DC supplied via the IO_VDD and IO_GND pins.
All output buffers, including the PCLK output, may be driven to a high-impedance
state if the RESET_TRST signal is asserted LOW.
Note that the timing characteristics of the parallel data output buffers are optimized
for 10-bit HD operation. As shown in
Figure 4-7
, the output data hold time for HD
is 1.5ns.
Due to this optimization, however, the output data hold time for SD data is so small
that the rising edge of the PCLK is nearly incident with the data transition. To
improve output hold time at SD rates, the PCLK output is inverted is SD mode,
(SD/HD = HIGH). This is shown in
Figure 4-8
.
Figure 4-7: HD PCLK to Data Timing
PCLK
DOUT[19:0]
DATA
Control signal
output
t
OH
t
OD
HD MODE
相關PDF資料 |
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| GS1559-CB | GS1559 HD-LINX-TM II Multi-Rate Deserializer with Loop-Through Cable Driver |
| GS1559-CBE2 | GS1559 HD-LINX-TM II Multi-Rate Deserializer with Loop-Through Cable Driver |
| GS2905 | 500mA CMOS LDO Voltage Regulator |
| GS2905X15 | 500mA CMOS LDO Voltage Regulator |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| GS1559_08 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:HD-LINX II Multi-Rate Deserializer with Loop-Through Cable Driver |
| GS1559-CB | 制造商:Semtech Corporation 功能描述: 制造商:Semtech Corporation 功能描述:HD/SD/ASI Receiver |
| GS1559CBE2 | 制造商:Gennum Corporation 功能描述:DESERIALISER HD/SDI/ASI W/DRV 100BGA 制造商:Gennum Corporation 功能描述:DESERIALISER, HD/SDI/ASI, W/DRV, 100BGA |
| GS1559-CBE2 | 功能描述:RF, RFID, WIRELESS RoHS:是 類別:集成電路 (IC) >> 接口 - 串行器，解串行器 系列:* 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 功能:解串器 數據速率:2.5Gbps 輸入類型:串行 輸出類型:并聯 輸入數:- 輸出數:24 電源電壓:1.8 V ~ 3.3 V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:64-TQFP 裸露焊盤 供應商設備封裝:64-TQFP-EP（10x10） 包裝:管件 |
| GS1560 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:HD-LINX II Voltage Controlled Oscillator |
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