- 您現在的位置：買賣IC網 > PDF目錄385323 > GS832418C-225I (GSI TECHNOLOGY) 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs PDF資料下載
參數資料
| 型號： | GS832418C-225I |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | DRAM |
| 英文描述： | 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs |
| 中文描述： | 2M X 18 CACHE SRAM, 6 ns, PBGA209 |
| 封裝： | 14 X 22 MM, 1 MM PITCH, BGA-209 |
| 文件頁數： | 15/46頁 |
| 文件大?。?/td> | 1149K |
| 代理商： | GS832418C-225I |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁當前第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁
Rev: 1.00 10/2001
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
15/46
2001, Giga Semiconductor, Inc.
Preliminary
GS832418(B/C)/GS832436(B/C)/GS832472(C)
Synchronous Truth Table (x72 and x36 209-Bump BGA)
Operation
Address Used
State
Diagram
Key
5
X
X
X
R
R
W
CR
CR
CW
CW
E
1
E
2
ADSP
ADSC
ADV
W
3
DQ
4
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Note:
1.
X = Don’t Care, H = High, L = Low.
2.
E = T (True) if E
2
= 1 and E
3
= 0; E = F (False) if E
2
= 0 or E
3
= 1.
3.
W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.
4.
G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown
as “Q” in the Truth Table above).
None
None
None
External
External
External
Next
Next
Next
Next
Current
Current
Current
Current
H
L
L
L
L
L
X
H
X
H
X
H
X
H
X
F
F
T
T
T
X
X
X
X
X
X
X
X
X
L
H
L
H
H
H
X
H
X
H
X
H
X
L
X
L
X
L
L
H
H
H
H
H
H
H
H
X
X
X
X
X
X
L
L
L
L
H
H
H
H
X
X
X
X
F
T
F
F
T
T
F
F
T
T
High-Z
High-Z
High-Z
Q
Q
D
Q
Q
D
D
Q
Q
D
D
5.
All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish
basic synchronous or synchronous burst operations and may be avoided for simplicity.
Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See
BOLD
items above.
Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See
ITALIC
items above.
6.
7.
相關PDF資料 |
PDF描述 |
|---|---|
| GS832418C-250 | 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs |
| GS832418C-250I | 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs |
| GS832436B-133 | 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs |
| GS832436B-133I | 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs |
| GS832436B-150 | 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs |
相關代理商/技術參數 |
參數描述 |
|---|---|
| GS8324Z36B-133 | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 2.5V/3.3V 36MBIT 1MX36 10NS/4NS 119FBGA - Trays |
| GS8324Z36B-200I | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 2.5V/3.3V 36MBIT 1MX36 7.5NS/3NS 119FBGA - Trays |
| GS8324Z72C200 | 制造商:G.S.I. 功能描述: |
| GS8342D06BD-350 | 制造商:GSI Technology 功能描述:165 FBGA - Bulk |
| GS8342D06BD-500 | 制造商:GSI Technology 功能描述:165 FBGA - Bulk |
發布緊急采購，3分鐘左右您將得到回復。