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參數(shù)資料
| 型號： | GS9092-CNE3 |
| 廠商： | Gennum Corporation |
| 英文描述： | GS9092 GenLINX-R III 270Mb/s Serializer for SDI and DVB-ASI |
| 中文描述： | GS9092 GenLINX - R的第三270Mb / s的串行SDI和DVB - ASI在內(nèi) |
| 文件頁數(shù)： | 10/58頁 |
| 文件大小： | 608K |
| 代理商： | GS9092-CNE3 |
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GS9092 Data Sheet
28202 - 2
September 2005
10 of 58
47
DVB_ASI
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS / LVTTL compatible.
When set HIGH by the application layer, the device will be configured
for the transmission of DVB-ASI data.The setting of the
SMPTE_BYPASS
pin will be ignored
.
When set LOW by the application layer, the device will not support the
encoding of DVB-ASI data.
49
SMPTE_BYPASS
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS / LVTTL compatible.
When set HIGH in conjunction with DVB_ASI = LOW, the device will be
configured to operate in SMPTE mode. All I/O processing features may
be enabled in this mode.
When set LOW, the device will not support the scrambling, encoding or
packet insertion of received SMPTE data. No I/O processing features
will be available and the device will enter a low-latency mode.
50
BLANK
Synchronous
with PCLK
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS / LVTTL compatible.
Functional only when chip is in SMPTE mode.
When set LOW by the application layer, the luma and chroma input
data is set to the appropriate blanking levels (TRS words will be
unaltered at all times)
When set HIGH by the application layer, the input data will pass into the
device unaltered.
51
DETECT_TRS
Non
Synchronous
Input
CONTOL SIGNAL INPUT
Signal levels are LVCMOS / LVTTL compatible.
Used to select external H,V, and F timing mode or TRS extraction
timing mode.
When set LOW by the application layer, the device will extract all
internal timing from the supplied H, V, and F timing signals.
When set HIGH by the application layer, the device will extract all
internal timing from the TRS signals embedded in the supplied video
stream. The H, V, and F signals will become outputs that can be
accessed via the STAT[2:0] pins.
Both 8-bit and 10-bit TRS code words will be identified by the device.
52
FIFO_EN
Non
Synchronous
Input
CONTOL SIGNAL INPUT
Signal levels are LVCMOS / LVTTL compatible.
Used to enable / disable the internal FIFO.
When FIFO_EN is HIGH, the internal FIFO will be enabled. Data will be
clocked into the device on the rising edge of the WR_CLK input pin if
the FIFO is in video mode or DVB-ASI mode.
When FIFO_EN is LOW, the internal FIFO is bypassed and parallel
data is clocked into the device on the rising edge of the PCLK input.
53
VCO_VDD
Analog
Input
Power
Power supply connection for Voltage-Controlled-Oscillator. Connect to
+1.8V DC.
54
LB_CONT
Analog
Input
CONTROL SIGNAL INPUT
Control voltage to fine-tune the loop bandwidth of the PLL.
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
Description
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| GS90A12-P1M | 功能描述:插入式交流適配器 80W 12V 6.67A RoHS:否 制造商:Phihong 地區(qū):Universal 安裝風(fēng)格:Wall, Interchangeable Plug 輸入電壓范圍:90 VAC to 264 VAC 輸出端數(shù)量:1 輸出功率額定值:5 W 輸出電壓（通道 1）:5 V 輸出電流（通道 1）:1 A 直流輸出連接器:USB Type A 隨附/必需的交流插頭:Required 商用/醫(yī)用:Commercial 效率:Level V |
| GS90A15-P1M | 功能描述:插入式交流適配器 90W 15V 6A RoHS:否 制造商:Phihong 地區(qū):Universal 安裝風(fēng)格:Wall, Interchangeable Plug 輸入電壓范圍:90 VAC to 264 VAC 輸出端數(shù)量:1 輸出功率額定值:5 W 輸出電壓（通道 1）:5 V 輸出電流（通道 1）:1 A 直流輸出連接器:USB Type A 隨附/必需的交流插頭:Required 商用/醫(yī)用:Commercial 效率:Level V |
| GS90A19-P1M | 功能描述:插入式交流適配器 90W 19V 4.74A RoHS:否 制造商:Phihong 地區(qū):Universal 安裝風(fēng)格:Wall, Interchangeable Plug 輸入電壓范圍:90 VAC to 264 VAC 輸出端數(shù)量:1 輸出功率額定值:5 W 輸出電壓（通道 1）:5 V 輸出電流（通道 1）:1 A 直流輸出連接器:USB Type A 隨附/必需的交流插頭:Required 商用/醫(yī)用:Commercial 效率:Level V |
| GS90A24-P1M | 功能描述:插入式交流適配器 90W 24V 3.75A RoHS:否 制造商:Phihong 地區(qū):Universal 安裝風(fēng)格:Wall, Interchangeable Plug 輸入電壓范圍:90 VAC to 264 VAC 輸出端數(shù)量:1 輸出功率額定值:5 W 輸出電壓（通道 1）:5 V 輸出電流（通道 1）:1 A 直流輸出連接器:USB Type A 隨附/必需的交流插頭:Required 商用/醫(yī)用:Commercial 效率:Level V |
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