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參數資料
| 型號： | GS9092-CNE3 |
| 廠商： | Gennum Corporation |
| 英文描述： | GS9092 GenLINX-R III 270Mb/s Serializer for SDI and DVB-ASI |
| 中文描述： | GS9092 GenLINX - R的第三270Mb / s的串行SDI和DVB - ASI在內 |
| 文件頁數： | 32/58頁 |
| 文件大小： | 608K |
| 代理商： | GS9092-CNE3 |
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GS9092 Data Sheet
28202 - 2
September 2005
32 of 58
3.3.4 Bypass Mode
The internal FIFO is in bypass mode when the application layer sets the FIFO_EN
or IOPROC_EN pin LOW, or the FIFO_MODE[1:0] bits in the IOPROC_DISABLE
register are configured to 11b. By default, the FIFO_MODE[1:0] bits are set to 11b
by the device whenever both the SMPTE_BYPASS and DVB_ASI pins are LOW;
however, the application layer may program the FIFO_MODE[1:0] bits as required.
In bypass mode, the FIFO is not inserted into the video path and data is presented
to the input of the device synchronously with the PCLK input. The FIFO will be
disabled and placed in static mode to save power.
3.4 SMPTE Mode
The GS9092 is said to be in SMPTE mode when the SMPTE_BYPASS pin is set
HIGH and the DVB_ASI pin is set LOW.
In this mode, the parallel data will be scrambled according to SMPTE 259M and
NRZ-to-NRZI encoded prior to serialization.
3.4.1 I/O Status Signals
When DETECT_TRS is LOW, the device will be locked to the externally supplied
H, V, and F signals. When DETECT_TRS is HIGH, the device will be locked to the
embedded TRS signals in the parallel input data. The H, V, and F pins become
output status signals, and their timing will be based on embedded TRS words.
3.4.2 HVF Timing Signal Inputs
As discussed above, the GS9092's internal flywheel may be locked to externally
provided H, V, and F signals when DETECT_TRS is set LOW by the application
layer.
The H signal timing may be configured via the H_CONFIG bit of the internal
IOPROC_DISABLE register as either active line-based blanking or TRS-based
blanking (see
Table 3-4
in
Packet Generation and Insertion on page 35
).
Active line-based blanking is enabled when the H_CONFIG bit is set LOW. In this
mode, the H input should be HIGH for the entire horizontal blanking period,
including the EAV and SAV TRS words. This is the default H timing assumed by
the device.
When H_CONFIG is set HIGH, TRS-based blanking is enabled. In this case, the H
input should be set HIGH for the entire horizontal blanking period as indicated by
the H bit in the associated TRS words.
The timing of these signals is shown in
Figure 3-8
.
When the DETECT_TRS pin is set HIGH, the output timing on the H pin can be
selected as either active line-based or TRS-based.
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