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參數資料
| 型號： | HD74CDC587 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 3.3-V Phase-lock Loop Clock Driver with 3-state Outputs(3.3-V 鎖相環時鐘驅動器) |
| 中文描述： | 3.3 - V相位鎖3環路時鐘驅動器狀態輸出（3.3 V的鎖相環時鐘驅動器） |
| 文件頁數： | 1/13頁 |
| 文件大小： | 79K |
| 代理商： | HD74CDC587 |
HD74CDC587
3.3-V Phase-lock Loop Clock Driver with 3-state Outputs
Preliminary
1st. Edition
September 1997
Description
The HD74CDC587 is a high-performance, low-skew, low-jitter, phase-locked loop (PLL) clock driver. It
uses a PLL to precisely align, in both frequency and phase, the clock output signals to the clock input
(CLKIN) signal. The HD74CDC587 operates at 3.3-V V
CC
and provides LVTTL- or SSTL_3- compatible
inputs and outputs. The HD74CDC587 operates at frequencies from 50 MHz up to 150 MHz, and is
ideally suited for high speed microprocessor and synchronous DRAM applications.
A dedicated feedback output (FBOUT) is used to synchronize the output clocks in frequency and phase to
the CLKIN reference. Four banks of four outputs (1Yn, 2Yn, 3Yn, 4Yn) are configured to operate at the
same frequency (1
×
) as the CLKIN. For proper operation, all SELn (n = 0, 1, 2, 3) inputs must be
externally tied to logic low.
The output enable (
OE
) input provides control for the Y output banks. When
OE
is high, the outputs are in
a high impedance state. When
OE
is low, the outputs switch at (1
×
) the CLKIN frequency. In addition,
RESET
provides a master reset for the HD74CDC587 counter circuitry. This allows the outputs to be reset
to a known state. TEST provides a bypass of the integrated PLL and divider circuitry. When TEST is
high, the input clock bypasses the PLL and is buffered directly to the outputs.
The loop filter components of the PLL are integrated on the HD74CDC587. This reduces the need for
external loop components and provides an easily implemented PLL circuit. FBOUT should be connected
to the feedback input (FBIN) for normal operation of the PLL.
The voltage-controlled oscillator (VCO) of the integrated PLL has an operating range of 100 MHz to 300
MHz. The VCO is designed to operate at twice (2
×
) the CLKIN frequency. This allows the HD74CDC587
to achieve output frequencies from 50 MHz to 150 MHz with a duty cycle of 50%
±
10% ensured.
Independent analog V
CC
(AV
CC
) and ground (AGND) connections are provided for VCO stability.
CLKIN and FBIN can be configured to switch at SSTL_3 input levels by connecting V
REF
to a nominal
reference voltage of 1.5 V. If V
REF
is strapped to GND, CLKIN and FBIN switch at normal TTL input
thresholds.
Because the HD74CDC587 is based on PLL technology, it requires a stabilization time to active phase lock
of the FBIN to the reference input clock. This stabilization time is required following power up and
application of a fixed-frequency, fixed-phase signal at CLKIN. In addition, a stabilization time may be
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